39 Cadence Innovus Jobs

Job Description Role Summary We are seeking a strategic and technically hands-on leader to drive end-to-end Physical Design execution across multiple design centers in APAC. The ideal candidate will combine deep technical mastery in implementation flows with proven experience managing distributed teams toward predictable execution, industry-leading PPA (Performance, Power, Area), and first-silicon success. Key Responsibilities Leadership & Strategy Define and execute a long-term physical design strategy aligned with business and product goals. Build, mentor, and scale a world-class PD organization across APAC sites (Hyderabad, Singapore, etc.). Champion flow automation, design methodology in...

Physical Design Engineer Location: Bengaluru, India Experience: 6+ years About the Role We are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust chip-level power, performance, and area (PPA) optimization. Key Responsibilities Execute full-chip and block-level physical design using Cadence Innovus, from floorplanning to GDSII. Perform timing closure, power optimization, and signal integrity analysis at advanced technology nodes. Conduct EM/IR (EMIR) analysis and sign-off to ensure robus...

Best Nanotech is expanding its VLSI team in Bengaluru ! We are looking for a Senior Physical Design Engineer with 7+ years of experience to take ownership of complex high-speed blocks from Netlist to GDSII in advanced technology nodes (5nm/3nm). Position: Senior/Lead Physical Design Engineer Location: Bengaluru (On-site/Hybrid) Experience: 7+ Years Your Impact: Ownership: Lead the complete PnR flow (Floorplan, Placement, CTS, Routing) for multi-million gate IP/SoC blocks. Closure: Drive timing, power, and physical signoff (DRC/LVS) to convergence. Optimization: Solve complex congestion, IR drop, and signal integrity issues in FinFET technologies. Mentorship: Guide junior engineers on flow me...

Director- Physical Design About Semifive Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea's semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions. SEMIFIVE's core business is its innovative SoC Platform that enables low-cost and high-efficiency SoC design, and also provides full turnkey design services for global customers through its diverse network. As the cost of developing an SoC and the demand for customized silicon continue to grow rapidly, SEMIFIVE's SoC Platform will play a key r...

#Urgent_Opening_for_Canvendor #Hiring: PD Floor Plan Engineer (5+ years) | Noida| Immediate Joiners Preferred Location: Noida, India Experience: 5+ years Notice period: Immediate #Key_Requirements: Own and drive floorplanning for complex SoC or IP blocks from RTL to GDSII. Collaborate with RTL, DFT, and architecture teams to understand design requirements and translate them into optimal floorplans. Perform macro placement , power grid planning , pin placement , and block-level partitioning . Analyze and optimize for congestion , timing , area , and power . Work closely with place & route , clock tree synthesis , and timing closure teams to ensure floorplan quality. Required Skills: Strong ha...

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and Twitter (X). Job Description: Principal Digital Physical Design Engineer Role Overview A Princ...

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop solutions and ensure performance requirements are met. **Roles and Responsibilities:** - Develop, integrate, and release new features in the high-performance place-and-route CAD flow - Architect and recommend methodology improvements for optimal power, performance, and area - Maintain, support, and debug implementation flows, resolving project-specific issues - Collaborate with worldwide CPU ph...

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach w...

As a PD CAD Engineer at our company, your role involves developing and supporting automated physical design (PD) CAD flows, which includes floorplanning, placement, and routing optimization. You will be responsible for customizing and optimizing physical design flows using industry-standard EDA tools like Synopsys Fusion Compiler and Cadence Innovus. Collaborating with the design and CAD teams is crucial to improve PD workflows and ensure a robust and efficient flow from RTL to GDSII. Your tasks will also include implementing automation scripts using TCL, Perl, and Python to enhance flow reliability and reduce design cycle time. Additionally, performing tool evaluations and benchmarking to k...

Position: ASIC Physical Design Engineer Location: Bangalore, India Employment Type: Long Term Contract Minimum Experience: 4 Years+ About the Role We are seeking a highly skilled ASIC Physical Design Engineer. The ideal candidate will have strong hands-on experience in P&R, STA, and synthesis tools, along with a deep understanding of modern technology nodes and design challenges. Key Responsibilities Perform floor planning, placement, CTS, routing, and sign-off using industry-standard tools. Drive timing closure, power optimization, and design convergence across advanced nodes. Execute static timing analysis (STA), support synthesis, and collaborate with RTL and DFT teams. Run DFT, IR-drop a...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to ...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to ...

As a Hardware Engineer at Qualcomm India Private Limited, your role involves planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge products. You will work on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. Key Responsibilities: - Perform Physical Implementation activities for high-performance Cores for various technologies such as 16/14/7/5nm or lower - Tasks may include floor-planning, place and route, clock tree synthesis, for...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis, formal verification, physical verification (DRC/LVS), power delivery network, timing closure, and power optimization. You will need to have a good understanding of PD implementation of PPA critical cores and be able to make appropriate PPA trade-off decisions. Additionally, knowledge in timing convergence of high-frequency data-path intensive cores and advanced STA concepts is essential. You should also be proficient in block-level PnR convergence with tools like Synopsys ICC2/Cade...

As a Physical Design Leader at Baya Systems, you will play a crucial role in revolutionizing semiconductor design with chiplet-based, high-performance modular systems. Your responsibilities will include tasks such as floor planning, clock tree synthesis, place-and-route, and timing closure activities for advanced technology nodes. You will collaborate cross-functionally with RTL designers, verification teams, and DFT engineers to ensure successful tape-outs. Your expertise in physical design tasks, EDA tools, timing closure, clock tree synthesis, low-power design methodologies, scripting languages, power integrity, and thermal optimization will be essential in overseeing the physical impleme...

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach w...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Job Requirements At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better placeto make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Key Responsibilities Key Responsibilities: Delivery Leadership Lead the Define and drive end-to-end RTL-to-GDSII flows, tai...

Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level) Active participation in post silicon validation, correlation and test activities using in-house test and validation lab Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow Perform custom RF Physical Design, including block-level and top level layouts...

As a senior physical design engineer, your role involves mentoring and coaching junior team members throughout the design process. You will provide technical guidance and support, ensuring optimal design quality and performance. Your responsibilities include: - Reviewing and providing feedback on floorplans, placement, and routing strategies. - Guiding the team in achieving timing closure targets through effective analysis and optimization techniques. - Collaborating with cross-functional teams to address design challenges and meet project goals. - Developing and maintaining best practices for physical design implementation. - Staying updated with industry trends and advancements in physical...

Back Lead Physical Design Engineer Bangalore, India 10+ Full-Time We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages...

Job Description: Broadcom is looking for a staff level physical design engineer. In this highly visible role, you will be contributing to ASIC for Storage/ AI products. Qualifications: Education and Experience : Master's degree in Electronics/Computer Engineering with over 10 years of experience in physical design. Physical Design Expertise : Extensive experience in Place & Route using Synopsys FC or Cadence Innovus tools is essential. Proficiency in STA using Primetime and/or Tempus. Demonstrated knowledge of Clock Tree Implementation Techniques for High-Speed Design Implementation. Ability to drive front-end and back-end implementation from RTL to GDSII, including synthesis, formal verific...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis (CTS), formal verification, physical verification (DRC/LVS), power delivery network (PDN), timing closure, and power optimization. Your role will involve making PPA trade-off decisions for critical cores, ensuring timing convergence of high-frequency data-path intensive cores, and implementing advanced STA concepts. You will work on block-level PnR convergence using tools like Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. Additio...

Job Title: Physical Design Engineer Experience: 4+ Years Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure. Key Responsibilities: Own block-level or full-chip implementation from RTL to GDSII. Perform: Floorplanning and placement Clock tree synthesis (CTS) Routing and optimization Run and close timing (STA), IR drop, EM, DRC, LVS, and a...