21 Cadence Innovus Jobs

Job Requirements At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better placeto make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Key Responsibilities Key Responsibilities: Delivery Leadership Lead the Define and drive end-to-end RTL-to-GDSII flows, tai...

Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level) Active participation in post silicon validation, correlation and test activities using in-house test and validation lab Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow Perform custom RF Physical Design, including block-level and top level layouts...

As a senior physical design engineer, your role involves mentoring and coaching junior team members throughout the design process. You will provide technical guidance and support, ensuring optimal design quality and performance. Your responsibilities include: - Reviewing and providing feedback on floorplans, placement, and routing strategies. - Guiding the team in achieving timing closure targets through effective analysis and optimization techniques. - Collaborating with cross-functional teams to address design challenges and meet project goals. - Developing and maintaining best practices for physical design implementation. - Staying updated with industry trends and advancements in physical...

Back Lead Physical Design Engineer Bangalore, India 10+ Full-Time We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages...

Job Description: Broadcom is looking for a staff level physical design engineer. In this highly visible role, you will be contributing to ASIC for Storage/ AI products. Qualifications: Education and Experience : Master's degree in Electronics/Computer Engineering with over 10 years of experience in physical design. Physical Design Expertise : Extensive experience in Place & Route using Synopsys FC or Cadence Innovus tools is essential. Proficiency in STA using Primetime and/or Tempus. Demonstrated knowledge of Clock Tree Implementation Techniques for High-Speed Design Implementation. Ability to drive front-end and back-end implementation from RTL to GDSII, including synthesis, formal verific...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis (CTS), formal verification, physical verification (DRC/LVS), power delivery network (PDN), timing closure, and power optimization. Your role will involve making PPA trade-off decisions for critical cores, ensuring timing convergence of high-frequency data-path intensive cores, and implementing advanced STA concepts. You will work on block-level PnR convergence using tools like Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. Additio...

Job Title: Physical Design Engineer Experience: 4+ Years Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure. Key Responsibilities: Own block-level or full-chip implementation from RTL to GDSII. Perform: Floorplanning and placement Clock tree synthesis (CTS) Routing and optimization Run and close timing (STA), IR drop, EM, DRC, LVS, and a...

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwid...

Hiring Senior VLSI Engineer (10+ yrs) with strong experience in Low-Power Implementation, EMIR Analysis (Static/Dynamic), and SoC Physical Design using Redhawk/Voltus, ICC2/Innovus. Required Candidate profile Experienced SoC PD engineer skilled in EMIR, low-power design, PnR, STA, DRC/LVS, and sign-off. Strong in TCL/Perl scripting, tool automation, and FinFET node implementation.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing, and physical verification. The role also involves collaborating with cross-functional teams, mentoring junior engineers, and ensuring design meets performance, power, and area specifications. Qualifications Strong expertise in flo...

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. Meet the Team Join a dynamic Physical Design team that drives end-to-end SoC implementation, from RTL to ...

At AMD, we are dedicated to transforming lives with our cutting-edge technology to make a positive impact on our industry, communities, and the world. Our goal is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. Central to our mission is the AMD culture, where we continuously strive for innovation to address the world's most pressing challenges. We are committed to achieving excellence in execution while upholding values of directness, humility, collaboration, and inclusivity of diverse perspectives. As a SOC Physical Design Director at AMD, you will play a ...

Physical Implementation activities for Sub systems include Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. You should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Your expertise should include timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. You should be well-versed with Block level PnR convergence using Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. A good understanding of clocking architecture is essential. Collaboration with design, DFT, and PNR tea...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or ...

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required...

Back Lead Physical Design Engineer Bangalore, India 10+ Full-Time We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages...

Qualcomm India Private Limited is looking for a CPU Physical Design CAD Engineer to join the Engineering Group, specifically in the Hardware Engineering department. As part of NUVIA that is now a part of Qualcomm, you will be at the forefront of reimagining silicon and creating cutting-edge computing platforms. Collaborate with a team of highly skilled engineers to design innovative solutions that redefine performance, energy efficiency, and scalability. To be considered for this role, you should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of experience in Hardware Engineering. Alternatively, a Mas...

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvells custom Processor/ASIC solution offers a differentiated ...

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurtur...

Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level) Active participation in post silicon validation, correlation and test activities using in-house test and validation lab Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow Perform custom RF Physical Design, including block-level and top level layouts...

Job Description: We are seeking an experienced Physical Design Engineer with strong expertise in VCLP (Voltage-Controlled Low Power) techniques and full flow RTL to GDSII implementation. Key Responsibilities: End-to-end ownership of physical design flow from RTL to GDSII VCLP implementation and optimization (highly important) Block-level and full-chip physical design Perform timing analysis , DRC/LVS checks , and power optimization Collaborate with front-end, verification, and DFT teams for successful tape-out Must-Have Skills: Strong hands-on experience in VCLP RTL to GDSII implementation EDA tools (Cadence Innovus, Synopsys ICC2, PrimeTime, Mentor Calibre) Scripting languages: Python, TCL,...