Posted:-1 days ago|
Platform:
Work from Office
Full Time
We are looking for an experienced STA Engineer who has successfully executed multiple tape-outs with hands-on expertise in timing closure and constraint handling. The candidate should possess strong knowledge of static timing analysis, ECO cycles, and power optimization methodologies.
Perform STA across multiple modes and corners.
Work on setup, hold, DRV and timing fixes across tools such as Synopsys PrimeTime, Cadence Tempus, Synopsys Tweaker, etc.
Handle timing constraints and clocks, generated clocks, IO delays, false paths, and multi-cycle paths.
Drive timing closure for blocks and full-chip sign-off.
Execute ECO cycles to achieve timing/performance targets.
Implement and validate power optimization techniques during design flow.
Collaborate with Physical Design, RTL, and Architecture teams for timing closure.
Strong understanding of STA and timing concepts.
Experience in timing closure for multiple tape-outs.
Expertise in Synopsys/Cadence STA tools.
Knowledge of power optimization techniques.
Good problem-solving, debugging, and cross-functional communication skills.
B.E / B.Tech / M.Tech in ECE, Electrical, VLSI, or related field.
Exiger Technologies
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