About the job Responsibilities Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic EDA team. Enable EDA flows and ensure tools are qualified on cutting edge IPs before rolling them to the wider community. Develops, maintains, debugs and tests SOC Design Methodologies using Commercial EDA tools Defines and creates flows/scripts to help design teams execute Front-End (RTL) to Back-End (GDS) flows seamlessly Take ownership, lead project and deliver results while guiding other engineers Verify CAD flows are generating correct results (flow signoff) and setup tool regressions Work closely with Engg IT and Database Mgmt teams to setup flows which work well with the Engineering Compute Infra in MaxLinear Datacenters Drive consensus across business units on tool & design methodology Work closely with technology and design teams to resolve signoff criteria Support design engineers on the flow setup and resolve their queries Qualifications MS/BS in Electrical/Computer Engineering with demonstrated experience in CAD or EDA tools flows architecture, development and support Demonstrated experience with various EDA software, flows and architectures & driving EDA vendors to improve tools to implement new functionality to solve problems or to optimize existing methods Must have worked on Digital flows/methodologies development in the domain of PD or DV. Should have proficient skills with one of PD related tools Genus/ Innovus /Tempus/ Calibre /FC/PT/DC. ( Or ) Should have proficient skills with one of DV related tools Xcelium /Questa/VCS/ vManager or equivalent. Must have strong scripting abilities in Python and/or Perl, tcl ; Must have UNIX knowledge and experience with data-management software Must have experience in taking ownership, leading projects along with guiding other engineers and producing results Ability to document design methodologies & provide training on tools and workflows to design teams Experience with Front-end Digital Design and/or PD and/or Digital Verification methodologies with a focus on digital and mixed-signal solutions Experience in defining and developing PD flow methodologies using Cadence/Synopsys/Siemens tools Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment Show more Show less
Job Summary: We are seeking a highly experienced Senior Physical Design Engineer with over 10 years of experience in the RTL to GDS flow. This full-time role will be based in Bangalore Karnataka. The ideal candidate will possess strong scripting skills, have hands-on experience with 3nm, 5nm nodes, and have a proven track record in physical design. Key Responsibilities Physical design efforts from RTL to GDS, ensuring high-quality and timely delivery of projects Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification Develop and maintain scripts for automation of physical design tasks, improving efficiency and reliability Collaborate with RTL designers, DFT engineers, and verification teams to resolve design issues and achieve timing closure Conduct power, performance, and area (PPA) optimization to meet design specifications Review and analyze physical design reports, including timing, signal integrity, and power analysis, and implement necessary changes Mentor and guide junior engineers, fostering a culture of knowledge sharing and continuous improvement Stay updated with the latest advancements in physical design tools and methodologies, and integrate best practices into the design process .Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field 10+ years of experience in physical design, with a comprehensive understanding of the RTL to GDS flow Hands-on experience with 3nm, 5nm process nodes Expertise in physical design tools such as Cadence Innovus, Synopsys ICC2, or similar Strong proficiency in scripting languages such as Tcl, Perl, or Python for automation of design tasks Proven experience in achieving timing closure, optimizing for PPA, and resolving complex design issues Solid understanding of digital design principles, including clock distribution, signal integrity, and power analysis Excellent problem-solving skills and attention to detail Strong communication skills, with the ability to work effectively in a team environment and collaborate with cross-functional teams .Preferred Skills Knowledge of low-power design techniques and methodologies Familiarity with version control systems and collaborative development tools Experience with physical verification tools such as Calibre or Mentor Graphics .
Job Summary: We are seeking a skilled STA Engineer with a strong background in Test and DFT architectures. The ideal candidate will have hands-on experience evaluating and writing high-quality timing constraints (SDCs) and performing thorough timing checks across complex digital designs. Key Responsibilities: Analyze and validate timing constraints (SDC) for DFT architectures. Develop and maintain accurate SDC files to support timing closure. Collaborate with design and test teams to ensure timing integrity across scan, BIST, and other test modes. Perform timing checks and quality assessments to identify and resolve constraint-related issues. Contribute to the development of best practices for DFT timing constraint generation and validation. Required Qualifications: Proven experience in STA with a focus on DFT/test modes. Strong understanding of DFT architectures and their impact on timing. Proficiency in writing and debugging SDCs. Familiarity with industry-standard STA tools (e.g., PrimeTime, Tempus). Excellent problem-solving and communication skills. Preferred Qualifications: Experience with scan insertion, ATPG, and BIST flows. Knowledge of RTL design and synthesis flows. Exposure to timing ECOs and constraint refinement.
About the Role This is a hybrid IT role supporting semiconductor development workflows. It sits between traditional IT and engineering, focusing on optimizing infrastructure for high-performance compute environments used in silicon design. You’ll collaborate with internal teams to ensure compute, storage, and networking resources are provisioned, maintained, and tailored to engineering needs. Responsibilities Coordinate with IT teams to provision and manage bare-metal and virtualized Linux servers, networked storage, and infrastructure upgrades Monitor and troubleshoot performance issues across hardware, software, storage, and networking systems Develop and maintain internal automation scripts (Perl, Python) to meet specialized engineering requirements Enforce data security policies and access controls Support engineers by diagnosing workflow-related issues and optimizing compute usage Analyze execution efficiency of EDA tools (e.g., Synopsys, Cadence, Siemens) Perform data extraction and reporting tasks Maintain and contribute to internal technical documentation (wiki-based) Requirements 5+ years of hands-on Linux experience, ideally with system administration exposure Proficiency in scripting (Perl, Python) Familiarity with IBM Spectrum LSF or similar workload management systems Strong written communication skills Nice-to-Have Skills Experience with cloud-based compute environments using LSF or similar tools Knowledge of NetApp NAS storage and NFS file systems Familiarity with automated build environments using make Exposure to semiconductor development tools (Verilog, logic synthesis, etc.) LDAP scripting experience (Vintela is a plus) Experience with Perforce version control Basic database skills (MySQL/MariaDB) and tactical database creation Dashboard development (HTML, Java, or other frameworks)
About the Role This is a hybrid IT role supporting semiconductor development workflows. It sits between traditional IT and engineering, focusing on optimizing infrastructure for high-performance compute environments used in silicon design. You'll collaborate with internal teams to ensure compute, storage, and networking resources are provisioned, maintained, and tailored to engineering needs. Responsibilities Coordinate with IT teams to provision and manage bare-metal and virtualized Linux servers, networked storage, and infrastructure upgrades Monitor and troubleshoot performance issues across hardware, software, storage, and networking systems Develop and maintain internal automation scripts (Perl, Python) to meet specialized engineering requirements Enforce data security policies and access controls Support engineers by diagnosing workflow-related issues and optimizing compute usage Analyze execution efficiency of EDA tools (e.g., Synopsys, Cadence, Siemens) Perform data extraction and reporting tasks Maintain and contribute to internal technical documentation (wiki-based) Requirements 5+ years of hands-on Linux experience, ideally with system administration exposure Proficiency in scripting (Perl, Python) Familiarity with IBM Spectrum LSF or similar workload management systems Strong written communication skills Nice-to-Have Skills Experience with cloud-based compute environments using LSF or similar tools Knowledge of NetApp NAS storage and NFS file systems Familiarity with automated build environments using make Exposure to semiconductor development tools (Verilog, logic synthesis, etc.) LDAP scripting experience (Vintela is a plus) Experience with Perforce version control Basic database skills (MySQL/MariaDB) and tactical database creation Dashboard development (HTML, Java, or other frameworks)