34 Cpf Jobs

Role & responsibilities • Define the product vision and roadmap for wealth platforms including Advent and Prospero. • Collaborate with stakeholders across Wealth Tribe, Investment Operations, and IT to gather and prioritize requirements. • Own the product backlog and ensure alignment with strategic goals and regulatory requirements (e.g., CPF Annual Regulation, Islamic proposition, ECM integration). • Lead Agile ceremonies and ensure timely delivery of features such as SIP workflows, trade settlement automation, and incremental load enhancements. • Coordinate with vendors for onboarding, Solutioning, and production support across Advent and Prospero platforms. • Monitor platform performance ...

Finance Control & Compliance professional Job Category: Finance Control & Compliances professional Job Type: Full Time Job Location: Bangalore Salary: 12-15lpa Years of Experience: 2-5yrs LinkedInFacebookTwitterEmailWhatsAppCopy LinkShare Position Summary: We are seeking a Finance Control & Compliance professional to join our Finance Team. Reporting to the Vice President, Finance, this role plays a critical part in ensuring adherence to financial controls, statutory compliance, and corporate governance across the APAC region. The ideal candidate will have strong expertise in internal controls, taxation (direct and indirect), secretarial compliance, and regulatory frameworks. This position re...

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwid...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and Twitter (X). Analog Devices Digital Business Unit (DBU) is seeking a Staff STA Engineer to lea...

Best Nanotech is expanding its VLSI team in Bengaluru ! We are looking for a Senior Physical Design Engineer with 7+ years of experience to take ownership of complex high-speed blocks from Netlist to GDSII in advanced technology nodes (5nm/3nm). Position: Senior/Lead Physical Design Engineer Location: Bengaluru (On-site/Hybrid) Experience: 7+ Years Your Impact: Ownership: Lead the complete PnR flow (Floorplan, Placement, CTS, Routing) for multi-million gate IP/SoC blocks. Closure: Drive timing, power, and physical signoff (DRC/LVS) to convergence. Optimization: Solve complex congestion, IR drop, and signal integrity issues in FinFET technologies. Mentorship: Guide junior engineers on flow me...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

As an Engineer at Qualcomm India Private Limited, your role will involve: - Defining chip and macro level power domains - Conducting System Level Power Modeling - Performing Mixed signal power analysis - Implementing Power Island/Power Gating/Power Isolation techniques - Designing Structural Low power components like level shifter and isolation cell topology - Analyzing and developing architectural solutions for digital power optimization logic/circuits/SW - Collaborating with Power Management IC developers for power grid planning - Creating detailed architecture and implementation documents Qualifications required for this role include: - Bachelor's degree in Computer Engineering and/or Ele...

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Customers around the world trust in our products and our application engineers significantly contribute to that. You are the first on the scene to address any technical problem. You are a competent adviser, great teammate, and make things possible. Unsolvable is a foreign term, and you don't do unfair. Your foc...

Job Title: Static Timing Analysis (STA) Engineer Job Overview We are looking for a highly skilled Static Timing Analysis (STA) Engineer to join our ASIC/SoC design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical expertise, problem-solving skills, and cross-functional collaboration. Key Responsibilities Perform Static Timing Analysis (setup, hold, recovery, removal) across all PVT corners and modes. Create, refine, and validate SDC constraints including clocks, generated clocks, false paths, and multi-cycle paths. Drive timing closure during synth...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

You will work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Your responsibilities will include: - Defining chip and macro level power domains - System Level Power Modeling - Mixed signal power analysis - Power Island/Power Gating/Power Isolation - Structural Low power design of level shifter and isolation cell topology and associated rules - Architectural analysis and development of digital power optimization logic/circuits/SW - Working with Power Management IC developers for power grid planning - Creating detailed architecture and implementation documents You should have at least 8-15 years of experience in the following areas: - Low power intent concepts a...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

We're looking for an experienced RTL Design Lead with strong leadership in front-end SoC design, from architecture to handoff. The ideal candidate will drive RTL design, integration, and synthesis, ensuring power, performance, and area efficiency while mentoring engineering teams. Key Responsibilities & Skills: * Lead RTL design from architecture definition to verified netlist delivery. * Own IP selection and configuration, balancing power, performance, and area trade-offs. * Hands-on experience in RTL design, verification, and synthesis with SoC IP integration. * Establish and maintain design flows: CDC, RDC, LINT, SDC, UPF/CPF. * Experience with physical synthesis and timing closure. * Und...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Job Summary We are seeking an experienced GLS Lead to drive gate level simulation activities, including power-aware GLS, formal verification, and MCP verification. The ideal candidate will lead a team of engineers, ensuring timely delivery of all verification projects and maintaining high quality standards. Key Responsibilities Lead and manage the GLS team, providing technical direction and mentorship. Plan, execute, and oversee gate level simulation (GLS) flows for complex SoC designs. Drive power-aware GLS and ensure coverage of low power verification scenarios. Overs...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Lead Design Verification Engineer Location: Chennai Experience: 5 to 10 Years Job Description: Develop and execute verification plans for complex SoC designs and IP blocks. Architect and implement testbenches using System Verilog and UVM/OVM methodologies. Perform RTL verification, simulation, and debugging. Collaborate with design, architecture, and software teams to ensure functional correctness. Contribute to IP design reviews and sign-off processes. Support post-silicon validation and bring-up activities. Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance. Conduct CPU subsystem verification (ARM/RISCV) including coherency...

Preferred candidate profile 5+ years of experience in Switch systems Lead and developer role please share profiles Switch migration and Switch implementation developer experience in EPF classic and UPF EPS - should have experience in EPS classic and UPF good communication

Hiring Senior VLSI Engineer (10+ yrs) with strong experience in Low-Power Implementation, EMIR Analysis (Static/Dynamic), and SoC Physical Design using Redhawk/Voltus, ICC2/Innovus. Required Candidate profile Experienced SoC PD engineer skilled in EMIR, low-power design, PnR, STA, DRC/LVS, and sign-off. Strong in TCL/Perl scripting, tool automation, and FinFET node implementation.

As a CPF Relationship Manager, you will play a crucial front-line role in our practice, upholding our commitment to comprehensive, reliable, and impactful financial planning. Your success in this position hinges on your ability to establish yourself as a trusted anchor for our HNI/NRI clients, offering pragmatic and empathetic financial solutions while fostering our client-centric ethos. Key Responsibilities: - Engage with clients to gain insight into their financial aspirations, life objectives, and obstacles. - Provide well-structured, goal-oriented investment suggestions that align with clients" risk profiles. - Coordinate regular portfolio evaluations and ensure prompt service delivery. ...

As an Engineer at Qualcomm India Private Limited, your role involves defining chip and macro level power domains, performing system level power modeling, conducting mixed signal power analysis, implementing Power Island/Power Gating/Power Isolation techniques, and designing structural low power components like level shifters and isolation cell topology. You will also be responsible for architectural analysis and development of digital power optimization logic, circuits, and software. Collaborating with Power Management IC developers for power grid planning and creating detailed architecture and implementation documents will be key aspects of your job. Your qualifications should include a Bac...

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: ...

General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements Required: Bachelor's, Computer Engineering and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and ...