19 Cpf Jobs

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Job Summary We are seeking an experienced GLS Lead to drive gate level simulation activities, including power-aware GLS, formal verification, and MCP verification. The ideal candidate will lead a team of engineers, ensuring timely delivery of all verification projects and maintaining high quality standards. Key Responsibilities Lead and manage the GLS team, providing technical direction and mentorship. Plan, execute, and oversee gate level simulation (GLS) flows for complex SoC designs. Drive power-aware GLS and ensure coverage of low power verification scenarios. Overs...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Lead Design Verification Engineer Location: Chennai Experience: 5 to 10 Years Job Description: Develop and execute verification plans for complex SoC designs and IP blocks. Architect and implement testbenches using System Verilog and UVM/OVM methodologies. Perform RTL verification, simulation, and debugging. Collaborate with design, architecture, and software teams to ensure functional correctness. Contribute to IP design reviews and sign-off processes. Support post-silicon validation and bring-up activities. Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance. Conduct CPU subsystem verification (ARM/RISCV) including coherency...

Preferred candidate profile 5+ years of experience in Switch systems Lead and developer role please share profiles Switch migration and Switch implementation developer experience in EPF classic and UPF EPS - should have experience in EPS classic and UPF good communication

Hiring Senior VLSI Engineer (10+ yrs) with strong experience in Low-Power Implementation, EMIR Analysis (Static/Dynamic), and SoC Physical Design using Redhawk/Voltus, ICC2/Innovus. Required Candidate profile Experienced SoC PD engineer skilled in EMIR, low-power design, PnR, STA, DRC/LVS, and sign-off. Strong in TCL/Perl scripting, tool automation, and FinFET node implementation.

As a CPF Relationship Manager, you will play a crucial front-line role in our practice, upholding our commitment to comprehensive, reliable, and impactful financial planning. Your success in this position hinges on your ability to establish yourself as a trusted anchor for our HNI/NRI clients, offering pragmatic and empathetic financial solutions while fostering our client-centric ethos. Key Responsibilities: - Engage with clients to gain insight into their financial aspirations, life objectives, and obstacles. - Provide well-structured, goal-oriented investment suggestions that align with clients" risk profiles. - Coordinate regular portfolio evaluations and ensure prompt service delivery. ...

As an Engineer at Qualcomm India Private Limited, your role involves defining chip and macro level power domains, performing system level power modeling, conducting mixed signal power analysis, implementing Power Island/Power Gating/Power Isolation techniques, and designing structural low power components like level shifters and isolation cell topology. You will also be responsible for architectural analysis and development of digital power optimization logic, circuits, and software. Collaborating with Power Management IC developers for power grid planning and creating detailed architecture and implementation documents will be key aspects of your job. Your qualifications should include a Bac...

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: ...

General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements Required: Bachelor's, Computer Engineering and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and ...

As the Financial Reporting/Fund Accounting VP, you will be responsible for leading financial reporting activities to ensure accuracy and timeliness. Your main focus will be managing a large team that specializes in statutory and regulatory reports. To excel in this role, you should have at least 10 years of experience in fund accounting or financial reporting, along with expertise in applying IFRS and US GAAP. Holding a CA, CPF, or MBA (Finance) would be advantageous. In your position as a Financial Reporting Vice President within the JP Morgan Financial Reporting Team, you will play a key role in coordinating financial reporting activities. Your primary objective will be to ensure the timel...

About SiFive SiFive is at the forefront of introducing RISC-V to the global landscape, revolutionizing the future of computing by harnessing the boundless potential of RISC-V for the most high-performance and data-intensive applications worldwide. SiFive's unparalleled computing platforms are empowering leading technology firms across diverse market segments such as artificial intelligence, machine learning, automotive, data center, mobile, and consumer electronics to innovate and deliver cutting-edge solutions. With SiFive, the horizon of possibilities with RISC-V knows no bounds. At SiFive, we are enthusiastic about engaging with individuals who share our zeal for driving innovation and ma...

At Cadence, we are looking for a dedicated individual to join our team as a Training Engineer. In this role, you will collaborate with product engineers, customer support, and R&D to identify training needs. Your responsibilities will include developing training materials such as lectures, labs, exams, and demos in alignment with software updates while maintaining high quality standards. As a Training Engineer, you will be involved in creating online and classroom-based training modules, delivering courses in various settings, and producing educational videos to guide customers on tool usage and methodologies. You will also provide support to online training participants and address any quer...

Qualcomm India Private Limited is seeking an experienced professional to join their Engineering Group in the Hardware Engineering area. In this role, you will collaborate with cross-functional teams to work on System on Chip (SoC) Power and architecture for mobile SoC Application-Specific Integrated Circuits (ASICs). To be successful in this position, you should have a minimum of 4-12 years of experience in the following key areas: - Familiarity with low power intent concepts and languages such as UPF or CPF - Proficiency in power estimation and reduction tools like PowerArtist/PTPX and Calypto - Understanding of power dissipation and power savings techniques, including dynamic clock and vol...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electri...

Key Responsibilities: Payroll Operations: Execute payroll operations in compliance with procedures, regulations, and customer requirements Process payroll data in accordance with legal and data protection standards. Ensure timely and accurate payroll processing and validation of transactions. Contribute to SOPs, training materials, and policy updates. Monitor quality, provide feedback, and participate in process improvements. Process payroll payments and initiate treasury releases. Collaborate with the Country Lead on local authority queries. Support accounting functions and manage payroll-related queries. Communicate risks and report payroll activity status. Support year-end and country-spe...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineeri...

Role & responsibilities Physical Design Engineer (PD/STA/Synthesis) Must-Haves: •Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA •Flow Experience: •Floorplanning •Power planning •Placement •Clock Tree Synthesis (CTS) •Routing •Physical Verification (DRC/LVS) •Timing Closure •Knowledge of: •Low-power design (UPF/CPF) •ECOs •IR Drop, EM Analysis •STA constraints and timing analysis Nice-to-Haves: •Experience with block-level and/or full-chip PD •Familiarity with scripting (Tcl, Perl, Python)

We are looking for a highly experienced DFT Lead Engineer to take ownership of Design-for-Test (DFT) architecture, implementation, and sign-off for complex flat SoC designs. This role requires deep expertise in PNR (Place-and-Route) within Cadence flow. Key Responsibilities Lead DFT strategy and implementation for flat SoC designs from RTL through tape-out. Develop and integrate test architectures including scan insertion, MBIST, LBIST, JTAG, and boundary scan. Work closely with the PNR team to ensure DFT structures are timing- and placement-aware. Drive test mode constraint creation and ensure compatibility with functional modes. Perform gate-level simulations for test logic verification. O...