STA Lead MediaTek India Technology Private Limited

5.0 - 7.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Description : KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnR <-> STA and timely feedbacks to PD team Generating block level HS session and using Top context from SoC for Block-SoC Interface timing closure. Generating timing ECO using Tweaker/PrimeClosure. Job Requirement: PREFERRED EXPERIENCE: 5+ years of experience in timing closure of high frequency blocks (> GHz range) Analyzing the timing reports and identifying both design and constraints related issues. Worked on blocks with multiple power and voltage domains Preferred EDA tool experience: Primetime, Tweaker/PrimeClosure, Innovus Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation Strong understanding of SDC constraints, OCV,AOCV,POCV analysis Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering

Posted 3 days ago

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Synthesis/STA Semicon TechnoLabs

3.0 - 12.0 years

0 Lacs

karnataka

On-site

You will be joining a leading training institute in the semiconductor industry that is constantly seeking dedicated individuals who are enthusiastic about achieving excellence and eager to expand their knowledge. Our work environment is dynamic, fostering innovation and creativity, and we provide avenues for personal and professional growth through training programs, mentorship, and coaching. The position available is for Synthesis/STA in either Bengaluru or Noida with a requirement of 3-12 years of experience and a BTECH/MTECH qualification. Key Responsibilities: - Demonstrated proficiency in timing concepts and the ability to independently close timing of Block/SoC. - Hands-on experience in generating constraints. - Proficiency in Logical synthesis tools such as Design compiler/ Rc compiler. - Familiarity with Formal Verification and comfortable using LEC/formality tools. - Ability to generate and implement functional Ecos. - Experience in Pre-layout and Post layout timing analysis using industry standard tools like Primetime/ETS. - Hands-on experience in crosstalk timing closure. - Understanding of Path based analysis, AOCV, DMSA is advantageous. - Knowledge of the complete physical Design flow is considered a plus. If you are a self-driven, innovative individual with a strong commitment to excellence, we encourage you to submit your resume and cover letter to our HR department. Be part of our dedicated team of professionals and contribute to the advancement of the semiconductor industry.,

Posted 2 months ago

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STA Lead Team Computers

5.0 - 8.0 years

25 - 40 Lacs

bengaluru

Work from Office

We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations. Conduct MMMC (Multi-Mode, Multi-Corner) timing analysis, including OCV, AOCV, and POCV variations. Integrate timing reports from multiple blocks, perform hierarchical timing closure, and ensure sign-off compliance. Work with DFT teams to analyze scan shift and at-speed test timing . Automate report generation, violation tracking, and closure metrics using Tcl, Perl, or Python . Provide guidance on timing budgets for IP/block owners. Interface with foundries and EDA vendors to resolve tool and library issues.

Posted Date not available

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