6 Aocv Jobs

Job Title: Static Timing Analysis (STA) Engineer Job Overview We are looking for a highly skilled Static Timing Analysis (STA) Engineer to join our ASIC/SoC design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical expertise, problem-solving skills, and cross-functional collaboration. Key Responsibilities Perform Static Timing Analysis (setup, hold, recovery, removal) across all PVT corners and modes. Create, refine, and validate SDC constraints including clocks, generated clocks, false paths, and multi-cycle paths. Drive timing closure during synth...

As an experienced ASIC/SoC designer with 3-5 years of experience, you will be responsible for the following key responsibilities: - Definition and development of signoff methodology and corresponding implementation solution. - Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. - Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC. - Streamlining the timing signoff criterions, timing analysis methodologies and flows. - Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. - Collaborate with Systems and Architecture, So...

Title: Physical Design Lead (PnR, STA) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Job Summary The individual will reports into the Design Methodology group and will be part of a team that is responsible for the creation of Design Methodology solutions for a wide variety of ...

Job Description : KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnR <-> STA and timely feedbacks to PD team Generating block level HS session and using Top context from SoC for Block-SoC Interface timing closure. Generating timing ECO using Tweaker/PrimeClosure. Job Requirement: PREFERRED EXPERIENCE: 5+ years of experience in timing closure of high frequency blocks (> GHz range) Analyzing the timing reports and identifying both design and constraints related issues. Worked on...

You will be joining a leading training institute in the semiconductor industry that is constantly seeking dedicated individuals who are enthusiastic about achieving excellence and eager to expand their knowledge. Our work environment is dynamic, fostering innovation and creativity, and we provide avenues for personal and professional growth through training programs, mentorship, and coaching. The position available is for Synthesis/STA in either Bengaluru or Noida with a requirement of 3-12 years of experience and a BTECH/MTECH qualification. Key Responsibilities: - Demonstrated proficiency in timing concepts and the ability to independently close timing of Block/SoC. - Hands-on experience i...

We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations. Conduct MMMC (Mul...