11 Full Chip Jobs

Responsibilities: Doing STD cells characterization work (max up to 40% of time) , Static timing analysis (60%) • Able to characterize basic STD Cells • Writing ARC for STD cell char (using primeLib , Silicon smart).lib QA check • Circuit understanding block wise , Full chip level • Static timing Analysis of DRAM block wise , top level analysis , cell level analysis • Writing constraints , analyzing the STA reports • Reporting violations to Design team , ownership for closure • Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions • Performing verification processes with modeling and simulation using industry standard simulators • Contribut...

Role : Senior STA Engineer Experience Required : 4-5 YEARS Job Location: HYDERABAD Bachelors or Masters degree in Electrical/Electronics Engineering. Preferred Qualifications: Experience with full-chip STA closure. Exposure to low-power design techniques and multi-mode/multi-corner analysis. Knowledge of timing integration for third-party IPs. Required Skills: Strong understanding of STA fundamentals and timing closure methodologies. Proficiency in tools like PrimeTime, Tempus, Tweaker, Timevision, Fishtail. Experience with scripting languages (TCL, Perl, Python) for automation. Familiarity with advanced nodes (e.g., 7nm, 5nm, FinFET). Good grasp of physical design flow and constraints manag...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

Role & responsibilities : * Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy. * Test Case Development: Develop stimulus and test cases to increase the functional coverage for DRAM, SRAM, and other emerging memory technologies. Core Requirements: * Strong Communication Skills: Ability to collaborate effectively within a team. * Leadership: Guide new team members and engineers, sharing your knowledge and experience. * Analytical Expertise: Deep understanding of complex CMOS and/or gate-level circuit designs. * Proficiency in SPICE and/or Verilog simulations. Preferred candidate profile : Required Skills: * Experience with SystemVeril...

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Co...

The role requires you to execute small to mid-size customer projects in various fields of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will be responsible for owning specific tasks related to RTL Design/Module and providing support to junior engineers in areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. It is crucial to independently analyze and complete assigned tasks within the defined domain successfully and on-time, ensuring on-time quality delivery approved by the project lead/manager. You will be evaluated based on the quality of deliverables, timely delivery, reduction...

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Co...