7 Rtl Synthesis Jobs

Siemens EDA is a global technology leader in Electronic Design Automation software, enabling companies worldwide to develop innovative electronic products efficiently. Customers utilize Siemens EDA's tools to drive technological advancements in chip, board, and system design within a complex landscape. Based in Bengaluru, this role offers opportunities to travel to various locations in India and globally, providing exposure to diverse projects that impact cities, countries, and future innovations. As part of the team, your responsibilities include deploying Siemens EDA ProFPGA prototyping software and hardware solutions at customer sites, ensuring successful design implementation. Collaboration with the R&D team is essential to address challenges, enhance product specifications, and develop effective solutions. Additionally, training Application Engineers (AEs) and customers on the solutions, winning pre-sales engagements, and supporting early customer deployments are key aspects of this role. Your role also involves maximizing customer value by developing methodologies that leverage the solutions" capabilities, keeping customers informed of the latest enhancements, and providing valuable insights to the R&D and marketing teams. Collaboration with Quality Assurance (QA) and Documentation (Docs) teams to improve testing and documentation processes is crucial, along with creating examples and tutorials for product delivery. The ideal candidate possesses a deep understanding of FPGA-based hardware prototyping platforms, multi-FPGA prototyping flows, and practical application of FPGA prototyping systems. Proficiency in HDLs (Verilog/SV) for RTL design, HVLs (SV/UVM) for verification, functional verification, RTL synthesis, and PnR flows is required. Familiarity with SoC design concepts, test bench acceleration, hardware/software debug solutions, and excellent communication skills are also essential. Siemens is a diverse community of over 377,000 individuals across 200 countries, united in building the future each day. The company values equality and encourages applications that reflect the diversity of the communities it serves. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Join Siemens Software in shaping tomorrow's innovations where today meets tomorrow.,

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of whats next in electronics and the world. Job Description Location: NOIDA Exp-7-15Y We are seeking a highly skilled & experienced Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Synthesis & STA flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in Synthesis & STA domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain Good understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, Conformal Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can do attitude,?openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier . At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make peoples lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark Join Renesas. Lets Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Responsibilities for this role include: We are working on the next generation RTL-to-GDSII solution. You should be able to completely own and drive the design and development of various pieces of the RTL synthesis technology, logic optimizations and low power synthesis. Experience and Qualifications: 5-8 years of proven experience in software development. B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college. Good knowledge of C/C++, algorithm and data structures. Good problem solving and analytical skills. Ability to guide and lead others, towards project completion. Desirable: We are looking for an individual with previous experience in RTL synthesis tool development. Knowledge of Verilog, VHDL, and formal verification. Expertise in RTL and gate-level logic, area, timing, and power optimizations. Familiarity with parallel algorithms and job distribution techniques. Proficiency in scripting languages like Python and Tcl. Communication Proficiency in English with strong interpersonal and excellent oral and written communication skills. Ability to collaborate as part of globally distributed team. Also, Self-motivated and able to work independently. We thrive on building a multi-functional team environment, and we look for individuals who are eager to contribute and grow with us!

8-12 years of proven experience in software development. Guide and lead team members towards successful project completion. Work with algorithms and data structures to design efficient solutions. Ensure high-quality code delivery through problem-solving and analytical skills. Collaborate effectively in a multi-functional team environment. Qualifications B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college. Good knowledge of C/C++, algorithms, and data structures. Strong problem-solving and analytical skills. Proven ability to guide and lead teams towards project completion. Desirable Previous experience in RTL synthesis tool development. Knowledge of Verilog, VHDL, and formal verification. Expertise in RTL and gate-level logic, area, timing, and power optimizations. Familiarity with parallel algorithms and job distribution techniques. Proficiency in scripting languages like Python and Tcl. Communication Skills Proficiency in English with strong interpersonal and excellent oral and written communication skills. Ability to collaborate as part of a globally distributed team. Self-motivated and able to work independently.

Job Title : FPGA Backend Engineer Experience : 3 to 6 Years Location : Bangalore Notice Period : Immediate to 15 Days Job Description : We are looking for a highly motivated FPGA Backend Engineer with 36 years of experience to join our engineering team in Bangalore . The ideal candidate will be responsible for implementing and optimizing FPGA designs from synthesis to bitstream generation, with a strong focus on timing closure and physical design. Key Responsibilities : Perform RTL synthesis and optimization using industry-standard tools (Vivado, Quartus, Synplify). Execute floorplanning, place & route (P&R) , and static timing analysis (STA) . Manage XDC/SDC constraint development for timing, clocks, I/O, and area. Conduct power and area analysis and apply optimization techniques. Run Design Rule Checks (DRC) and resolve physical implementation issues. Generate and validate bitstreams for FPGA deployment. Collaborate with RTL, verification, and system teams to ensure clean handoffs and design integrity. Maintain and automate flows using TCL, Python, or Shell scripts . Required Skills : Strong experience with FPGA backend flow (Synthesis, STA, P&R). Good understanding of FPGA architecture (preferably Xilinx or Intel). Proficiency in XDC/SDC constraints , timing reports, and debugging violations. Experience with TCL scripting and automation of implementation flows. Familiarity with Verilog/VHDL for understanding RTL structure. Hands-on experience with tools like Vivado, Quartus, Synplify, TimeQuest . Ability to work independently and drive tasks to closure. Nice to Have : Exposure to multi-clock domain designs and CDC analysis . Experience in timing closure for high-speed interfaces. Knowledge of low-power design techniques in FPGA. Experience with version control systems (e.g., Git). Why Join Us? Opportunity to work on cutting-edge FPGA projects. Fast-paced and technically challenging environment. Collaborative team and growth-focused culture. Job Details : Position Type : Full-Time / Permanent Work Location : Bangalore (Hybrid/On-site depending on project needs) Joining Requirement : Candidates with Immediate to 15 Days notice preferred

A minimum of 8 years of related experience. Excellent Software development experience with C / C++ on UNIX/Linux platforms Broad understanding of data structures, algorithms and their applications. Should have experience working in a multi-person product development environment with high dependencies and tight schedules. It is essential that the applicant is highly motivated and has solid desire to learn and explore new technologies. Demonstrated history of good analytical, debugging and problem-solving skills. Experience with complex software tool development and usage with legacy code base Exercise of judgment in developing methods, techniques, and evaluation criteria to meet project goals. Ability to work in both self-directed and collaborative settings. Understanding/Experience in Unified Power Format (UPF) would be beneficial Good written and oral communication skills, for team collaboration and product presentations. Preferred Skills: Special consideration given to those with background and experience in formal verification and/or synthesis techniques. Experience in Compilers and RTL Synthesis would be beneficial Knowledge of software specification and design process, and regression testing. Ability to know about customer wants and needs in the formal verification user community, by working with sales and field personnel.

Looking for Siemens EDA ambassadors This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/ EE/ ECE from a reputed engineering college with 8-12 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and TCL.