3 Rtl Synthesis Jobs

Job Title : FPGA Backend Engineer Experience : 3 to 6 Years Location : Bangalore Notice Period : Immediate to 15 Days Job Description : We are looking for a highly motivated FPGA Backend Engineer with 36 years of experience to join our engineering team in Bangalore . The ideal candidate will be responsible for implementing and optimizing FPGA designs from synthesis to bitstream generation, with a strong focus on timing closure and physical design. Key Responsibilities : Perform RTL synthesis and optimization using industry-standard tools (Vivado, Quartus, Synplify). Execute floorplanning, place & route (P&R) , and static timing analysis (STA) . Manage XDC/SDC constraint development for timing, clocks, I/O, and area. Conduct power and area analysis and apply optimization techniques. Run Design Rule Checks (DRC) and resolve physical implementation issues. Generate and validate bitstreams for FPGA deployment. Collaborate with RTL, verification, and system teams to ensure clean handoffs and design integrity. Maintain and automate flows using TCL, Python, or Shell scripts . Required Skills : Strong experience with FPGA backend flow (Synthesis, STA, P&R). Good understanding of FPGA architecture (preferably Xilinx or Intel). Proficiency in XDC/SDC constraints , timing reports, and debugging violations. Experience with TCL scripting and automation of implementation flows. Familiarity with Verilog/VHDL for understanding RTL structure. Hands-on experience with tools like Vivado, Quartus, Synplify, TimeQuest . Ability to work independently and drive tasks to closure. Nice to Have : Exposure to multi-clock domain designs and CDC analysis . Experience in timing closure for high-speed interfaces. Knowledge of low-power design techniques in FPGA. Experience with version control systems (e.g., Git). Why Join Us? Opportunity to work on cutting-edge FPGA projects. Fast-paced and technically challenging environment. Collaborative team and growth-focused culture. Job Details : Position Type : Full-Time / Permanent Work Location : Bangalore (Hybrid/On-site depending on project needs) Joining Requirement : Candidates with Immediate to 15 Days notice preferred

A minimum of 8 years of related experience. Excellent Software development experience with C / C++ on UNIX/Linux platforms Broad understanding of data structures, algorithms and their applications. Should have experience working in a multi-person product development environment with high dependencies and tight schedules. It is essential that the applicant is highly motivated and has solid desire to learn and explore new technologies. Demonstrated history of good analytical, debugging and problem-solving skills. Experience with complex software tool development and usage with legacy code base Exercise of judgment in developing methods, techniques, and evaluation criteria to meet project goals. Ability to work in both self-directed and collaborative settings. Understanding/Experience in Unified Power Format (UPF) would be beneficial Good written and oral communication skills, for team collaboration and product presentations. Preferred Skills: Special consideration given to those with background and experience in formal verification and/or synthesis techniques. Experience in Compilers and RTL Synthesis would be beneficial Knowledge of software specification and design process, and regression testing. Ability to know about customer wants and needs in the formal verification user community, by working with sales and field personnel.

Looking for Siemens EDA ambassadors This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/ EE/ ECE from a reputed engineering college with 8-12 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and TCL.