1121 Dft Jobs - Page 20

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded Underpinning our mission is the AMD culture We push the limits of innovation to solve the worlds most important challenges We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives AMD together we advance_ LEAD SOFTWARE SYSTEMS DESIGN ENGINEER The Role AMD is looking for an experienced engineer for an exciting role in Server CPU software development team This person will be a member of a core team and will work with the latest hardware and software technology The person will interact closely with key AMD technical experts to ensure the best possible performance and results on AMD platforms The Person The successful candidate for this position will be interacting with software and hardware technologists working across many locations This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions Key Responsibilities Problem solving across multiple software layers, (user space, kernel, applications, libraries) and hardware Optimization/development of the CPU performance stack (applications, libraries) for AMD server and workstation processors on Windows platform Analyze and solve performance, scalability bottlenecks when code is running on multi-core, multi-node deployments Innovate and publish papers, patents and participate in technical conferences to advance AMD technologies Continuously learn and grow along with evolving X86 server CPU architecture and application landscape Preferred Experience Image processing skills: Color format conversions, Image Filtering and Enhancement operations, Morphological operations, Image transforms and statistical operations Good understanding in Image Detection, Segmentation, Recognition, Restoration and Medical Imaging Knowledge in Signal Processing theory like Sampling, Quantization, DFT and FFT Multi-threaded FFT computing, Distributed FFT computing Very strong data structure and algorithmic skills Experience in identifying performance bottlenecks, and designing/implementing optimizations to relieve analyzed bottlenecks Strong Windows internals with experience in software development using C/C++ and debugging skills on multicore systems (preferably using OpenMP) Experience in performance analysis for data center, HPC (High Performance Computing), MPI (Message passing Interface) applications Experience in x86 (or other architecture based) optimizations Understanding of Cache sub-system, Instruction Set Architecture, pipeline (for any CPU) Bonus skills: Experience on Intel MKL libraries, Linear Algebra, x86 assembly programming (vector/SIMD), porting source code from Linux to Windows, development on Windows servers Knowledge of one or more CPU Profiling tools (preferably in Windows) Academic Credentials Graduate/masters degree in computer science or related fields LOCATION: Bangalore Benefits offered are described: AMD benefits at a glance AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law We encourage applications from all qualified candidates and will accommodate applicantsneeds under the respective laws throughout all stages of the recruitment and selection process

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company: Did you know KONE moves two billion people every day? As a global leader in the elevator and escalator industry, we employ over 60,000 driven professionals in more than 60 countries worldwide joined together by a shared purpose, to shape the future of cities. In 2023, we had annual net sales of EUR 11.0 billion. Why this role? We are seeking for an Associate Engineer - Electronics supports the design, testing, and implementation of electronic systems and components. This role involves hands-on work with circuit design, embedded systems, and electronic testing, under the guidance of senior engineers. Ideal for candidates with foundational knowledge in electronics and a drive to innovate. What will you be doing? Assist in the design and development of analog and digital electronic circuits. Doing designs with KONE Electronics Design Automation tools or any popular EDA tools in the industry Support testing, troubleshooting, and validation of electronic hardware and embedded systems. Prepare technical documentation, schematics, and test reports. Collaborate with cross-functional teams including mechanical, software, and manufacturing engineers. Conduct component selection and ensure compliance with industry standards. Participate in prototype development and field testing Required Skills: Exposure in Hardware Development Life Cycle (HDLC) Familiar with European & American codes for hardware design (IEC, IPC, EN and CSA etc). Knowledge in Board design on Analog Design, Digital design, microprocessor and microcontroller based design, Memory Interfaces Sound Knowledge on communication protocols like RS232, RS485, SPI, CAN etc Knowledge to EMI, EMC standards & DFM, DFT Knowledge in RF fundamental for design. Knowledge to PCB Design & Simulation tools for Circuit design and analysis. Are you the one? Bachelor’s degree in Electronics/Electrical/Communication/Instrumentation Engineering or related discipline. 1–3 years of experience in electronics design or testing (internships included). Familiarity with EDA tools such as Cadence OrCad, Zuken Cadstar, Zuken CR8000, Cadence OrCAD PSPICE, LTSPICE, SI/PI, DFx etc… Familiarity / Basic Hands on with Lab Equipments - MSO/DSO, Logic analyser, Thermal, High end Power supplies etc… Problem solving skills, Self Learning attitude, Good Communication, Analytical & Presentation skills. What do we offer? Development and growth opportunities within a global organization. Warm and friendly international working environment, covering Being part of an industry leader in sustainability. At KONE, we are focused on creating an innovative and collaborative working culture where we value the contribution of each individual. Employee engagement is a key focus area for us and we encourage participation and the sharing of information and ideas. Sustainability is an integral part of our culture and the daily practice. We follow ethical business practices and we seek to develop a culture of working together where co-workers trust and respect each other and good performance is recognized. In being a great place to work, we are proud to offer a range of experiences and opportunities that will help you to achieve your career and personal goals and enable you to live a healthy and balanced life. Read more on www.kone.com/careers

Company Description Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi-billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics. Job Description  Full PE product lifecycle ownership from concept to end of life with a focus on ensuring the delivery of the highest quality products to our end customers  Definition of ATE test, qualification and manufacturing plans  Product release into manufacturing with adherence to stringent tier 1-customer requirements  Datasheet and automotive compliance reports  Real time customer support for design, product and quality related issues  Temperature/Voltage/Process characterization and production limit setting  Product new product introduction and yield ownership  Product BOM release and maintenance  Excursion management for both suppliers and customers  Use commercially available yield tools for yield improvement and monitoring, generate weekly reports and review with PE teams  KPI achievement in product related deliverables including NPI execution and velocity, product cost (Gross margin improvements), product quality performance and failure analysis cycle times  PAT, SYL, SBL, SPC limit and disposition optimizations to protect quality without excessive waste Requirements  7+ years experience in product engineering. A strong analog circuit background is a must. Familiarity with power management IC testing would be a plus  Familiarity with ATE tester platforms (eg. Teradyne J750, Advantest 93K)  Knowledge of analog and mix-signal circuitry and the common building blocks, device physics, test methodology and DFT knowledge  Experience with common lab test equipment (DC power supply, oscilloscope, multi- meters etc). Bench characterization experience is a plus  Familiarity with JEDEC/AEC qualification standards and stress test conditions. Experience with qual hardware/software development would be preferred  Experience in yield management tools such as PDF Exensio, JMP. Apply statistical analysis to isolate the issue and make data-driven decisions  Ability to managing supplier excursions and customer escalations through problem solving  Knowledge of Semiconductor Failure Analysis is preferable  Strong verbal and written communication skills  A good team player. Effective in fast paced, dynamic work environment

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG In depth knowledge of DFT concepts. In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. Expertise in scripting languages such as perl, shell, etc. Experience in simulating test vectors. Knowledge of equivalence check and RTL lint tool (like spyglass). Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076259

About Vecmcon: Vecmocon was incubated in 2016 at IIT Delhi by Peeyush Asati (CEO), Adarshkumar Balaraman (COO) and Shivam Wankhede (CTO). The company has now established its presence in major cities including Delhi, Bangalore, Chennai & Lucknow with a passionate team of more than 180 associates. The company is at the forefront of advanced computing solutions for electric mobility, specializing in safety-critical components such as Battery Management Systems (BMS), EV chargers, Vehicle Intelligence Modules (VIM), secure Firmware Over the Air (FOTA), etc for electric vehicles. The company is working with two of the top 5 EV players in India and various leading battery manufacturers ensuring a high level of reliability and safety, delivering robust performance for the next generation of intelligent and smart EVs. With a vision to develop the most reliable, robust, and cost-efficient systems, Vecmocon aims to drive the mass adoption of electric vehicles globally. About Role: We’re seeking a Senior PCB Design Engineer to lead the design and development of PCBs for chargers used in electric two and three-wheelers. The role requires deep expertise in PCB design, strong hardware fundamentals, component selection skills, and a solid understanding of power electronics and PCB manufacturing. Roles and Responsibilities: Lead design of high-reliability power electronics PCBs for automotive-grade products Own schematic creation, stack-up definition, and material selection for high-current, high-voltage designs Ensure compliance with EMI/EMC, thermal, and mechanical constraints during layout Conduct architecture reviews and design validation with the hardware team Select components based on electrical, thermal, cost, and reliability trade-offs Review and maintain schematic symbols, footprints, and library standards Lead root cause analysis for validation and production-level PCB issues Release complete production documentation (Gerbers, BoM, pick-and-place, assembly drawings) Guide junior engineers and drive best practices in layout and design Coordinate with suppliers and manufacturers for DFM/DFA compliance Implement cost reduction and continuous improvement based on field feedback Support ICT and FCT processes Ski lls 3+ years of PCB design experience; proficiency in Altium Designer preferred Strong foundation in electrical engineering and power electronics Expertise in analog, digital, and power layout with good thermal design practices Experience in debugging and testing power electronics systems Familiar with IPC standards (IPC-2221, IPC-2152, IPC-4761) and DFM/DFT guidelines Knowledge of signal/power integrity, impedance control, and EMI/EMC compliance Understanding of mechanical constraints; experience with 3D CAD models (DXF/STEP) Strong documentation and communication skills Leadership abilities to mentor and manage junior team members

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: Program Manager 1 THE ROLE: We are seeking an experienced and dynamic Program Manager to join our Custom ASIC/SOC Development Group. In this role, you will lead high-impact technical programs from concept through tapeout to post-silicon validation. You’ll manage cross-functional execution across RTL, verification, physical design, packaging, and bring-up, delivering complex SoC solutions to our global partners. THE PERSON: This role is ideal for someone with a strong technical background in chip design and 3–5 years of program management experience, capable of managing complexity, influencing stakeholders, and driving results in a highly matrixed organization. KEY RESPONSIBILITIES Own and drive SoC program execution from requirements through tapeout. Develop detailed plans of record, schedule, deliverables, resources, risks, and mitigation strategies. Coordinate across IP, SoC front-end, back-end, validation, test, and packaging teams. Act as the central point of contact for program status, issues, risks, and escalations—internally and externally. Monitor and communicate progress using dashboards, KPIs, Gantt charts, and performance metrics. Ensure quality gates are met and engineering change requests are tracked and resolved promptly. Collaborate with engineering leads to make technical tradeoffs and align with design goals. Facilitate executive reporting and program reviews. Promote best practices in program execution and risk management. PREFERRED EXPERIENCE: Experience in managing multiple SoC programs in domains like mobile, compute, automotive, AI, etc. PMP certification or equivalent program/project management training. Familiarity with program tools such as MS Project, JIRA, Confluence, Power BI, or equivalent. Executive communication experience and ability to influence across technical and business functions. REQUIRED QUALIFICATIONS: Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Science Engineering. 10-12+ years of experience in the semiconductor industry with 3–5 years in technical program management. Strong hands-on exposure in SoC design flows, IP development, integration, Verification/Validation, DFT, STA, physical design, and tapeout. Proven track record in leading cross-functional, geographically dispersed teams. Strong risk and issue management capabilities, with the ability to escalate and drive resolution effectively. #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Designation: Electrical Design Engineering Experience: 5+ Years Roles & Responsibilities:- Lead the architecture, design, and validation of power converters and electrical hardware platforms. Perform feasibility studies, design calculations, thermal analysis, and component selection. Conduct detailed PCB layout reviews Ensure IPC compliance, signal and power integrity, and manufacturing best practices, Identify and correct layout faults and cosmetic issues. Collaborate with outsourcing partners for hardware design and manufacturing execution. Drive hardware integration, ensuring system-level electrical performance. Focus on innovation initiatives including new converter topologies, design optimizations, and reliability enhancements. Lead technical design reviews, mentor junior engineers, and define internal hardware standards. Support EMC testing, HALT/HASS reliability testing, and regulatory compliance. Key Result Areas: Delivery of robust, high-efficiency power and control hardware architectures. Advancement of innovation initiatives within hardware development. Quality assurance and management of outsourced design and manufacturing partners. Development and enforcement of internal hardware review frameworks and documentation standards. Technical leadership and capability building across the hardware engineering team. Internal: Lead the delivery of high-efficiency power and control hardware architectures across projects. Drive innovation initiatives such as new converter topologies, design optimization, and advanced reliability methods. Establish and enforce hardware review frameworks, DFM/DFT standards, and documentation practices. Mentor and develop internal engineering capabilities through technical leadership and structured reviews. External: Manage collaboration with outsourcing partners for hardware design, manufacturing, and validation. Ensure outsourced work meets internal quality standards, design specifications, and timeline requirements. Lead technical reviews of externally developed designs for IPC compliance, manufacturability, and signal integrity. Coordinate with external suppliers and manufacturers to secure customized components and ensure smooth prototype and production deliveries. Educational Qualification: •Bachelor's or Master’s degree in Electrical Engineering, preferably with specialization in Power Electronics. Required Skills: Expertise in power converter design across major topologies. Strong proficiency in digital and analog control circuit design. Extensive experience in PCB layout reviews emphasizing signal integrity, power distribution, and IPC compliance. Practical knowledge of Design for Manufacturing (DFM) and Design for Testability (DFT). Hands-on with PCB CAD tools (Altium Designer, Cadence Allegro) and Signal Integrity simulation software. Vendor management experience for external hardware development. Strong leadership, technical documentation, communication, and mentoring abilities.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Program Manager 1 The Role We are seeking an experienced and dynamic Program Manager to join our Custom ASIC/SOC Development Group. In this role, you will lead high-impact technical programs from concept through tapeout to post-silicon validation. You’ll manage cross-functional execution across RTL, verification, physical design, packaging, and bring-up, delivering complex SoC solutions to our global partners. The Person This role is ideal for someone with a strong technical background in chip design and 3-5 years of program management experience, capable of managing complexity, influencing stakeholders, and driving results in a highly matrixed organization. Key Responsibilities Own and drive SoC program execution from requirements through tapeout. Develop detailed plans of record, schedule, deliverables, resources, risks, and mitigation strategies. Coordinate across IP, SoC front-end, back-end, validation, test, and packaging teams. Act as the central point of contact for program status, issues, risks, and escalations—internally and externally. Monitor and communicate progress using dashboards, KPIs, Gantt charts, and performance metrics. Ensure quality gates are met and engineering change requests are tracked and resolved promptly. Collaborate with engineering leads to make technical tradeoffs and align with design goals. Facilitate executive reporting and program reviews. Promote best practices in program execution and risk management. Preferred Experience Experience in managing multiple SoC programs in domains like mobile, compute, automotive, AI, etc. PMP certification or equivalent program/project management training. Familiarity with program tools such as MS Project, JIRA, Confluence, Power BI, or equivalent. Executive communication experience and ability to influence across technical and business functions. Required Qualifications Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Science Engineering. 10-12+ years of experience in the semiconductor industry with 3-5 years in technical program management. Strong hands-on exposure in SoC design flows, IP development, integration, Verification/Validation, DFT, STA, physical design, and tapeout. Proven track record in leading cross-functional, geographically dispersed teams. Strong risk and issue management capabilities, with the ability to escalate and drive resolution effectively. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip s for full chip timing analysis. we'll aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus.

Experience in dft scan insertion, atpg at ip and soc level Hands on experience in atpg timing and no-timing simulations Proficient in doing basic unit-level verification using simulations. Scan/atpg patterns & test flows development, debug, test and characterization

Apply to this job The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Metas computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Metas data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl/Python, TCL, and Make About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures

Experience in Static Timing Analysis (STA) for ASIC designs Experience in developing timing constraints Experience in timing closure and optimization Proficiency in using scripting languages such as Perl and TCL Familiarity with EDA tools such as PrimeTime and Design Compiler Experience in Physical Design and/or DFT is a plus Bachelor s or Master s degree in Electrical/Electronics/Computer Science Engineering or related field

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job responsibilities: BE/BTECH/ME/MTECH Or Equivalent Degree Very good knowledge on SCAN/ATPG/JTAG/MBIST Experience with one or more chip tape out that includes chip ATE bring up. Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG) Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques. Experience in scan insertion techniques at block level and chip top level. Experience on Memory BIST generation, insertion, verification on RTL/Netlist level. Good knowledge and understanding in Analog PHY and Analog Macro tests. Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE1149.6 standards. Good knowledge on test mode timing constraints Good knowledge about running block level and chip STA flows. Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team. Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent tools) Experience with post-silicon bring up and debug on ATE. Good knowledge on Perl/Tcl scription skills Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization. High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project. Should have B-Tech/M-tech with 5 Years to 15 Years relevant experience. We’re doing work that matters. Help us solve what others can’t.

◆◆ HIRING – QUALITY MANAGER (PEB STRUCTURE ) ◆◆ Company : SModi Infrasteel Pvt. Ltd. Work Location : Rohad Industrial Area, Bahadurgarh Job Type : Full-Time | Permanent | Factory-Based Role Apply via Email : info@smodiinfrasteel.in HR Contact : +91 7042853529 ──────────────────────────────────── ▪︎ WHO WE ARE SModi Infrasteel Pvt. Ltd. is a steel building company that makes Pre-Engineered Buildings (PEB) – large sheds and warehouses made from factory-fabricated steel parts. These buildings are used by factories, logistic parks, cold storages, and industrial units. We make these steel parts inside our factory, transport them to the customer’s site, and assemble them there. ──────────────────────────────────── ▪︎ WHAT IS THIS JOB ABOUT? We are hiring a Quality Manager who will work our factory (in Rohad, Bahadurgarh). Your job is to check whether the steel parts being made are correct, strong, and ready to go to site. This includes checking steel cutting, welding, drilling, painting, and overall accuracy of the work. ──────────────────────────────────── ▪︎ WHAT WILL YOU DO? 1. Steel Material Checking (When it Enters Factory) Check if the steel plates, coils, angles, beams, and other raw material match the order. See if any material is damaged, bent, rusted, or low-quality. Match material test certificates (MTCs) with IS codes and customer specifications. 2. Fabrication Quality Checking Check how our team cuts and joins steel to make parts like columns, rafters, purlins, etc. Ensure all dimensions are exactly as per fabrication drawing (length, hole distance, thickness, angle). Use measuring tape, angle square, weld gauge, and calipers to confirm accuracy. Identify wrong cutting, wrong welding, or poor fitting and stop it on the spot. 3. Welding Inspection Confirm that welders are certified and are following the right welding procedure (WPS/PQR). Check welding joint strength, size, and cleanliness – no holes, cracks, or weak joints should be passed. Maintain welding inspection reports with welder name, joint type, and location. 4. Painting and Surface Finish Checking Check that steel parts are properly cleaned before primer/paint. Use DFT (dry film thickness) meter to ensure correct paint thickness. Ensure paint brand, number of coats, drying time, and finishing are as per project specs. Reject any part with paint bubbles, rust patches, or improper coating. 5. Documentation & Reporting Fill daily quality checklists (fit-up, welding, finishing, painting). Maintain records with photos of all inspection stages. Report problems to the Production Manager and get them corrected before dispatch. Coordinate with the dispatch team to ensure only approved material is sent to site. ──────────────────────────────────── ▪︎ WHO SHOULD APPLY? Education: Diploma or B. Tech in Mechanical or Civil Engineering Experience Needed: Minimum 5 to 10 years of experience in PEB work or steel fabrication shop Must know how to read steel drawings and understand fabrication steps Must have worked with welders, fabricators, painters, and dispatch teams Must know how to use basic QC tools: tape, weld gauge, DFT meter, spirit level, etc. ──────────────────────────────────── ▪︎ SALARY & WORK CONDITIONS Monthly Salary : ₹30,000 to ₹50,000 (based on experience) Tea & lunch break included Growth opportunity to become Head of Quality based on performance ──────────────────────────────────── ▪︎ WHY JOIN SMODI INFRASTEEL? Work with one of the most experienced companies in the PEB industry Get hands-on exposure to live fabrication & quality systems Be part of high-value projects across India Stable job with long-term growth and professional work culture ──────────────────────────────────── ▪︎ HOW TO APPLY? Send your updated CV to : info@smodiinfrasteel.in Call or WhatsApp HR at : +91 7042853529 ──────────────────────────────────── #Hiring #QualityManager #PEBJobs #SteelFabrication #PlantJobs #CivilEngineer #MechanicalEngineer #QAQC #RohadJobs #BahadurgarhJobs #FactoryWork #WeldingQC #FitupQC #PaintQC #PEBIndustry #SteelStructure #PEBQualityEngineer #QualityManagerPEB #SteelStructureJobs #PreEngineeredBuildings #FabricationQuality #WeldingInspector #SteelQC #PaintInspection #StructuralSteelJobs #FactoryJobs #QAQCJobs #QualityControlEngineer #QualityAssurance #PEBIndustry #IndustrialShedJobs #WarehouseConstruction #ErectionQuality #WPSPQR #WeldingQC #PaintingQC #SteelFabricationJobs #CivilEngineerJobs #MechanicalEngineerJobs #JobInBahadurgarh #RohadIndustrialArea #PlantBasedJob #ManufacturingQuality #HeavySteelFabrication #PEBCareer #SteelBuildingIndustry #SModiInfrasteel Job Types: Full-time, Permanent Pay: ₹30,000.00 - ₹50,000.00 per month Schedule: Day shift Morning shift Work Location: In person

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl/Python, TCL, and Make About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Overview: Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities: Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip’s for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications: Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

Meta is hiring talented individuals to join our Infrastructure organization as ASIC Frontend Implementation Engineers (RDC/CDC). In this role, you will play a critical part in designing and developing efficient System on Chip (SoC) and IP for data center applications. As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize your expertise in RTL Lint, CDC analysis, timing constraints, and synthesis to ensure seamless integration of various components to build efficient System on Chip (SoC) and IP for data center applications.By joining our team, you'll have the opportunity to contribute to the development of cutting-edge technology that powers Meta's infrastructure. ASIC Engineer, Frontend Implementation RDC/CDC Responsibilities: Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all Front End (FE)-tools including (Lint, CDC, RDC,) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location Preferred Qualifications: Scripting and programming experience using Perl/Python, TCL, and Make Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Experience with SOC Design Integration and Front-End Implementation Experience with developing structural rule based checks for RTL & Netlist Experience with Netlist-CDC Analysis and improving MTBF Knowledge of Timing/physical libraries, SRAM Memories About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Skills : Supervision and monitoring of work force, reviewing and Certifying all QA/QC documents, site procedures, and relevant codes of job application to the projects. Knowledge of satisfactory client relation management. Plans and develops work schedules, Tools and Equipment usage schedules, priority of painting expenditures and procedures for equipment maintenance Ensures all the safety regulations and adheres to proper codes and standards of application job. Inspection of Surface preparation, Planning daily work for sand blasters & painters, Control & storage of painting / coating consumables, Calibration & validation blasting and painting equipments, Qualification/Knowledge of coating processes, Atmospheric conditions, Monitoring of coating cycle, DFT, WFT, Adhesion, Holiday test etc. Inspect, check, and monitor all painting / coating related works and ensure all final products meet in accordance with company procedure, client requirement and International codes and standards. Familiar with different standards like NACE, SSPC, ISO. Education : Graduate Painting/Coating Inspector certification (preferred) NACE Level 1 Certified (preferred) Experience : 2-5 Years Language : Fluent in English and Hindi (If you think above job profile fits your profile, feel free to contact us.) Job Types: Full-time, Permanent Pay: ₹234,000.00 - ₹1,200,000.00 per year Benefits: Commuter assistance Health insurance Internet reimbursement Life insurance Paid time off Provident Fund Schedule: Day shift Supplemental Pay: Performance bonus Yearly bonus Application Question(s): Can you take proper measurements as per IS ? Education: Diploma (Preferred) Experience: Painting supervisor: 3 years (Preferred) Language: Fluent English & Hindi ? (Preferred) Work Location: In person

Skills : Reviewing and Certifying all QA/QC documents, site procedures, and relevant codes of job application to the projects. Inspection of Surface preparation, Planning daily work for sand blasters & painters, Control & storage of painting / coating consumables, Calibration & validation blasting and painting equipments, Qualification/Knowledge of coating processes, Atmospheric conditions, Monitoring of coating cycle, DFT, WFT, Adhesion, Holiday test etc. Inspect, check, and monitor all painting / coating related works and ensure all final products meet in accordance with company procedure, client requirement and International codes and standards. Familiar with different standards like NACE, SSPC, ISO. Knowledge of satisfactory client relation management. Plans and develops work schedules, Tools and Equipment usage schedules, priority of painting expenditures and procedures for equipment maintenance Ensures all the safety regulations and adheres to proper codes and standards of application job. Education : Graduate Painting/Coating Inspector certification (preferred) NACE Level 1 Certified (preferred) Experience : 2-5 Years Language : Fluent in English and Hindi (If you think above job profile fits your profile, feel free to contact us.) Job Types: Full-time, Permanent Pay: ₹234,000.00 - ₹1,400,000.00 per year Benefits: Commuter assistance Food provided Health insurance Internet reimbursement Life insurance Paid time off Provident Fund Schedule: Day shift Supplemental Pay: Performance bonus Yearly bonus License/Certification: NACE Certificate (Preferred) Work Location: In person

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles and Responsibilities Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. Work closely with design/verification teams within CPU to develop comprehensive test plan. Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. Verify power intent through use of methodologies like UPF. Work closely with system architects, software teams and Soc team to validate system use cases. Work closely with emulation team to enable verification on emulators and FPGA platforms. Debug and triage failures in simulation, emulation and/or Silicon. BE/BTech degree in CS/EE with 3+ years’ experience. Experience in power management verification. Implementation of assembly and C language embedded firmware. Experience in C/C++, scripting languages, Verilog/system Verilog. Strong understanding of power management features in CPUs and CPU based Socs. Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements Good Understanding of CPU architectures and CPU micro-architectures. In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture Experience with advanced verification techniques such as formal and assertions is a plus Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071121

Job Summary:We are seeking a hands-on and quality-driven Powder Coating Supervisor to manage daily operations of our powder coating line. The role involves overseeing the entire process from pre-treatment to curing, ensuring quality standards, safety compliance, and meeting production timelines. Key Responsibilities:Supervise day-to-day powder coating activities including surface preparation, pre-treatment, coating, and curing. Ensure proper chemical concentration, tank maintenance, and cleanliness in pre-treatment processes (e.g., 7-tank, chromate, phosphating). Coordinate with production and dispatch teams to meet deadlines and prioritize urgent jobs. Monitor and adjust spray equipment, booths, ovens, and powder guns to ensure consistent finish and thickness. Perform quality checks (DFT, adhesion, finish, color match) as per customer or internal specifications. Train and manage coating line workers, helpers, and QC staff. Maintain records of daily production, rework, and wastage. Implement and follow safety protocols and proper PPE usage. Coordinate with maintenance teams for preventive upkeep of powder coating equipment. Suggest process improvements for efficiency, cost reduction, and quality enhancement. Skills & Requirements:In-depth knowledge of powder coating process, equipment, and chemicals. Familiar with DFT gauges, gloss meters, and surface finish testing tools. Ability to read technical drawings and interpret surface finish specifications. Strong supervisory and communication skills. Working knowledge of ISO/TS standards, 5S, and lean practices preferred. Basic computer proficiency (Excel, report logging, etc.). Preferred Experience:Background in sheet metal, fabrication, automotive, or consumer durable industries. Experience with manual and automated powder coating lines. Exposure to audits and quality systems is a plus.

We are seeking an experienced design verification engineer with strong technical and leadership skills, who thrives in a fast-paced environment, to lead a talented team of engineers responsible for developing an efficient, scalable UVM based verification environment to exercise large, complex IP blocks. THE PERSON: In this role, you will lead a high-performance central design team through the full verification lifecycle of a state of-the-art industry leading Debug IP, from planning and implementing innovative verification strategies to collecting and closing coverage. You will establish a collaborative environment that fosters innovation and verification best practices. In addition to managing project schedules, deliverables, dependencies, and risk mitigation plans, you will mentor, provide technical guidance, and further develop the team. The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. A global mindset and ability to lead in a multi site environment are keys to being successful in this role. KEY RESPONSIBILITIES: Lead the CDFX DV team at AMD Bangalore Office to perform the Debug IP verification, which includes: IP level test plan creation and development, conducting and participating in test plan reviews developing scalable verification components, random-constrained stimulus, and debugging regression failures Code reviews and DV coverage analysis Provide technical guidance and innovative ideas to improve quality, processes, and productivity Manage DV execution: project planning, IP delivery timelines, deliverables and quality checks track project progress and ensure projects stay on track for timely completion resource planning, critical path analysis, risks identification and mitigation plan Technical support to SOC teams (internal customers) on Debug IP deliverables and tape out readiness signoff Collaborate with cross-functional leaders to drive AMDs success Strategic team development plan creation Team performance review and management Guide and develop people at several different levels of experience to encourage career growth Talent recruiting. Occasional short-term international travel upon per business need PREFERRED EXPERIENCE: Experience leading verification teams on complex CPU/ASIC projects from inception to tape-out Solid understanding of functional design verification, including but not limited to test bench architecture, coverage, random constrained testing, and debug. Excellent organizational and project management skills Proven experience managing and leading engineering teams Strong communications skills. Able to summarize complex problems for executives as we'll as drill down to details with architects and engineers Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments Must be a self-starter and self-motivated ACADEMIC CREDENTIALS: BTECH/BE/BS, MTECH/ME/MS, or PhD degree in Electrical or Computer engineering. Advance degree preferred.