1109 Dft Jobs - Page 17

Job Title: Embedded Hardware Development Engineer Location: Kolkata Employment Type: Full-time Experience Level: 1-3 years preferred About the Role We are looking for a motivated and skilled Embedded Hardware Development Engineer to join our R&D team focused on automotive IoT and vision-based telematics solutions. The role involves end-to-end hardware development—from architecture to prototype to production—for intelligent in-vehicle systems and connected mobility devices. Key Responsibilities Design and develop embedded hardware for automotive IoT devices, including telematics control units (TCUs), vision systems (e.g., ADAS cameras), and edge gateways. Create schematics and multilayer PCB layouts using tools like Altium Designer, KiCad, or Eagle. Select and evaluate components considering performance, cost, and automotive-grade certifications. Integrate various communication protocols including I2C, SPI, UART, CAN, LIN, and Ethernet. Work closely with the firmware and software teams for cross-functional development and validation. Support prototyping, board bring-up, debugging, and functional testing in lab and vehicle environments. Ensure compliance with automotive and industry standards (ISO 26262, AEC-Q100, EMI/EMC). Collaborate with suppliers and production teams for DFM/DFT and product industrialization. Document hardware designs, test results, and support certification processes. Required Skills and Qualifications B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, Instrumentation, or related field. 1+ years of hands-on experience in embedded hardware design, preferably in automotive or IoT domains. Strong understanding of microcontroller/microprocessor architectures (STM32, NXP, TI, Renesas, etc.). Proficient in hardware interface protocols like I2C, SPI, UART, CAN, and Ethernet. Experience in power supply design, battery-backed systems, and protection circuits. Skilled in using lab instruments such as oscilloscopes, logic analyzers, power analyzers, etc. Familiarity with PCB design, EMC best practices, and thermal management. Good to Have / Preferred Skills Exposure to vision systems, camera integration (MIPI CSI, FPD-Link, GMSL), and ADAS hardware. Experience working with GNSS, 4G/5G, Wi-Fi, and BLE modules. Understanding of automotive safety and quality standards (ISO 26262, IATF 16949). Basic understanding of embedded C/C++ and firmware debugging. Familiarity with OTA hardware requirements, secure boot, and hardware cryptography. Why Join Us Be part of the next generation of connected vehicle technology and smart mobility. Work on real-world, production-grade systems deployed in fleets. Friendly, fast-paced environment with freedom to innovate and grow. Opportunity to collaborate with multidisciplinary experts in embedded systems, vision, and cloud. Job Types: Full-time, Permanent Pay: Up to ₹50,000.00 per month Benefits: Cell phone reimbursement Provident Fund Schedule: Day shift Work Location: In person Speak with the employer +91 7595811717 Expected Start Date: 07/07/2025

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Ampere is seeking a highly skilled and experienced candidate with proven expertise in PHY hardening, particularly in DDR and SerDes, with a focus on digital implementation and convergence. We are looking for a self-motivated individual with a proven track record in hardening state-of-the-art PHYs and contributing to the development of cutting-edge expertise. What You’ll Achieve As a PHY Hardening Engineer, you will collaborate with architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. This is an exceptional opportunity to showcase your engineering skills in a dynamic, fast-paced environment that fosters innovation and operates at the forefront of technology. High-Speed Digital Design Develop high-speed digital layouts, including DDR and other high-speed interfaces. Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits. Optimize layouts to minimize signal integrity issues, reduce power consumption, and meet timing, power, and manufacturability requirements. Coordinate with PHY vendors for hardening activities and deliverables. Estimate effort and timelines for PHY hardening tasks and provide feedback on timing/PDV. Chip-Level Physical Design Perform chip-level tasks such as floor planning, partitioning, and power/clock distribution. Handle chip assembly and ensure seamless integration of multiple IP blocks into the top-level design. Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC). Collaborate with the packaging team to refine bump placement and package routing considerations. Signal and Power Integrity Familiarity with signal and power integrity concepts in high-performance memory systems. Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation. Perform thermal and power integrity analysis to ensure reliable designs. Knowledge of advanced packaging techniques and considerations, an added plus Design-for-Test (DFT) Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms. Contribute to DFT-based timing closure activities. About You Bachelor's degree & 8 years of related experience or Master's degree & 6 years of related experience Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits Experience developing high-speed digital layouts, including DDR and other high-speed interfaces Handling chip assembly and ensure seamless integration of multiple IP blocks into the top-level design Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC) Worked with architects and RTL teams to develop physical constraints and optimize their design Integrate PHYs, controllers, and memory stacks into the top-level design Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs Handle micro-bump design to ensure proper alignment and minimize resistance Understand the SIPI impacts of bump placement Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms Strong communication and articulation skills are required to excel in this role What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

We are seeking highly motivated and talented VLSI Engineers with 2-4 years of industry experience to join our intensive Campus Training Program. This program is designed to provide in-depth, hands-on training in various aspects of VLSI design, verification, and implementation, specifically tailored to align with our current projects and future technological advancements. Upon successful completion of the training, candidates will transition into key roles within our VLSI design teams. This is an excellent opportunity for engineers looking to deepen their expertise, specialize in cutting-edge VLSI methodologies, and contribute to the development of next-generation semiconductor products. Responsibilities during the Training Program: * Actively participate in structured training modules covering advanced VLSI concepts, methodologies, and tools. * Engage in hands-on lab sessions and practical exercises to apply learned concepts. * Collaborate with trainers and mentors on assigned projects and case studies. * Complete individual and group assignments, demonstrating understanding and proficiency in VLSI sub-domains. * Participate in technical discussions, design reviews, and knowledge-sharing sessions. * Learn and adhere to industry best practices, design flows, and quality standards. * Continuously seek to improve technical skills and knowledge through self-study and provided resources. * Document progress, learning outcomes, and project work thoroughly. Key Areas of Training (may include, but are not limited to): * Digital IC Design: Advanced RTL design, low-power design techniques, clock domain crossing (CDC). * Verification: Advanced UVM/SystemVerilog methodologies, functional coverage, formal verification. * Physical Design: Floorplanning, placement, routing, clock tree synthesis (CTS), static timing analysis (STA), power integrity (PI) analysis. * Design for Testability (DFT): Scan insertion, ATPG, boundary scan. * Analog/Mixed-Signal Design (if applicable): Device physics, circuit simulation, layout considerations. * Front-End Tools: Synthesis, Linting, STA. * Back-End Tools: Place and Route, DRC/LVS. * Scripting: Perl, Python, TCL for automation. * EDA Tools: Exposure to industry-standard EDA tools from Cadence, Synopsys, Mentor Graphics (specific tools will be taught based on company needs). Required Qualifications: * Bachelor's or Master's degree in Electronics and Communication Engineering (ECE), Electrical Engineering (EE), or a related field. * 2-4 years of professional experience in VLSI design, verification, or physical design. * Strong fundamental understanding of digital electronics, circuit theory, and semiconductor physics. * Proficiency in at least one hardware description language (HDL) such as Verilog or VHDL. * Familiarity with the VLSI design flow (front-end to back-end). * Experience with scripting languages (e.g., Python, Perl, TCL) is highly desirable. * Excellent problem-solving and analytical skills. * Strong communication and interpersonal skills. * Ability to learn quickly and adapt to new technologies and methodologies. * Self-motivated with a strong desire to build a long-term career in VLSI. Preferred Qualifications (Assets): * Prior experience with specific EDA tools (Cadence Virtuoso, Synopsys DC/ICC/VCS, Mentor Graphics Calibre, etc.). * Experience with UVM methodology for verification. * Understanding of low-power design techniques. * Familiarity with formal verification concepts. * Exposure to advanced technology nodes.

Job Description Seeking a highly motivated and innovative Senior digital design engineer with knowledge of ASIC development flow. As a Senior Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL synthesis and constraints generation/validation for MCU SoCs, ensuring they meet performance, power, and area specifications Develop and implement innovative implementation methodologies and tools to enhance productivity and design quality Be the bridge between Backend and Frontend teams to reconcile on hand-off and timing issues Conduct thorough design reviews and provide constructive feedback to peers and junior engineers Collaborate with cross-functional teams to not only resolve collateral issues but also to improve the overall PPA Support Low Power Implementation Support formality checks Preferred Experience Experience in owning RTL synthesis and constraints for complex IPs/SS/SoC Experience in owning or supporting STA at full-chip level Exposure to latest methodologies in constraints generation, promotion/demotion and validation Familiarity with Low Power Implementation flows Qualifications Required and Preferred Qualifications Required Bachelor's degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE degree and 12+ years of experience in IC design, or MSEE (or PhD) with 9+ years of experience and with a proven track record of delivering high-quality designs Experience with industry-standard EDA tools for synthesis, constraints validation and static timing analysis Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Ability to mentor and guide junior engineers in IC design best practices and methodologies Scripting experience in Shell, Perl, Python and TCL is a plus Good communication skills for interacting between different design groups cross functional groups are required Preferred Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Some level of understanding of DFT flows and steps Exposure to Automotive SoC designs Additional Information Soft Skills and Cultural Fit Exceptional problem-solving skills with the ability to analyse complex design challenges Proactive attitude with a commitment to continuous learning and professional development A collaborative mindset with the ability to thrive in a fast-paced, dynamic environment Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: Design Verification Engineer Location: Bangalore Work Type: Hybrid Job Type: Full time Job Description: Over 5 years of experience in Design verification. Good exposure to Subsystem and SOC level verification. UVM, System Verilog and C based verification environment. CDC and GLS exposure DFX and DFT verification experience Exposure to Complex SOCs. Experience in High-speed protocols like PCIe, Ethernet is add on. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Lead the architecture, design and development of a server class, high- performance Processor CPU for IBM Systems. - Architect and design Instruction caches, Branch Predictors, Issue queues, Register Renaming, Load Store Execution and other areas of the IBM processor CPU - Research novel instruction/data prefetching and branch prediction architectures. - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

- Lead the architecture, design and development of Instruction Sequencing Unit for high-performance Processor CPU of IBM Systems. - Architect and design Instruction Dispatch to Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Instruction Dispatch unit of CPU - Hands of experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of Instruction Decode and Execution units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise . 6 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. - Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise .12 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) - Hands on experience of different Branch Prediction techniques - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Knowledge of at least one object oriented or functional programming language and scripting language. - Nice to haves - Knowledge of instruction decode and handling pipeline hazards - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Lead the architecture, design and development of a server class, high- performance Processor CPU for IBM Systems. - Architect and design Instruction caches, Branch Predictors, Issue queues, Register Renaming, Load Store Execution and other areas of the IBM processor CPU - Research novel instruction/data prefetching and branch prediction architectures. - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

Lead the architecture, design and development of Processor Core Vector- Scalar Execution unit for high-performance IBM Systems. - Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise 12 or more years of demonstrated experience in architecting and designing Execution unit of CPU - Hands on experience of implementing Arithmetic/Crypto/SIMD functions - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and load/store units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Lead the architecture, design and development of Processor Core Load- Store Execution unit for high-performance IBM Systems. - Architect and design Load and Store pipelines, D-Cache, Address Translation, Out of Order Execution of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise 12 or more years of demonstrated experience in architecting and designing Load-Store Execution unit of CPU - Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and Arithmetic units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred Education

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Sr DFT Engineers and Managers - location remote any where in India Job Summary Our clients Arasan Chip Systems (www.arasan.com) based in US are seeking for their India Development Center Senior and Experienced DFT Engineer with 68 years of hands-on expertise in Design-for-Test methodologies and implementation for complex SoC designs. The candidate will be responsible for developing and integrating DFT architectures, driving ATPG and MBIST flows, and working closely with RTL design, physical design, and test teams to ensure high test coverage and silicon readiness. Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Generate and validate test patterns (stuck-at, transition, path delay). Collaborate with RTL, synthesis, and physical design teams to ensure DFT integration and timing closure. Participate in silicon bring-up and ATE support. Support internal reviews, audits, and DFT documentation. Skills Strong experience with industry-standard DFT tools (Mentor Tessent, Synopsys DFTMAX, Cadence Modus, etc.). Hands-on experience in scan insertion, ATPG, MBIST, boundary scan, and test compression techniques. Familiarity with ATE pattern generation and silicon debug flows. Solid understanding of RTL/gate-level simulation, synthesis, STA, and timing-aware DFT flows. Proficiency in scripting languages (TCL, Perl, Python) for automation. Excellent analytical and problem-solving skills. Qualifications B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field. 6–8 years of relevant experience in DFT for ASIC/SoC design. Preferred Exposure to low-power DFT methodologies (UPF/CPF flows). Prior experience with automotive or high-speed PHY IP integration is a plus. Knowledge of IEEE standards (1149.1, 1500, 1687).

Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Health insurance

Job Title Engineering Manager – Electrical Job Description Engineering Manager – Electrical In late January, we announced that Bridgefield Capital signed an agreement to acquire Philips’ Emergency Care business which includes leading brands and products like HeartStart AEDs, Intrepid and DFM100 monitor defibrillators, Tempus monitor and Tempus ALS systems, and Corsium and ECI informatics solutions. We expect the transaction to close at the end of 2025. With Bridgefield’s support and building on our 40+ year legacy of growth and innovation in emergency medical technology, the Emergency Care business will continue passionately pursuing our mission of saving lives, lowering the cost of healthcare, and advancing the science of resuscitation while serving the public access AED, EMS, military, and hospital market segments. In this role, you have the opportunity to Be an integral part of the Emergency Care and Resuscitation (ECR) R&D leadership team, actively participating in cardiac defibrillator product development. ECR team has a broad product portfolio of advanced life support solutions, automated external defibrillators, monitoring and data management solutions. Our mission is to design, produce, and deliver every solution as if the life of someone we love depends on it. Every day, we empower and enable our customers – from clinicians to paramedics, first responders to the everyman – to save lives using our innovative, market-leading technology. Your role: We are looking for a passionate Technical Engineering Manager-Electrical to join us as we strengthen our product portfolio, expand our services and solutions, and bring game-changing technology to the market. This team member will be responsible for working collaboratively with a team of cross-functional engineers. Lead, mentor, and grow a high-performing electrical engineering team. Drive performance management, talent development, and resource planning. Align team priorities with business strategy and R&D roadmaps. Manage program-level budget and resource allocation in collaboration with business stakeholders. Provide end-to-end ownership of electrical system design: requirements, schematics, PCB layout, testing, and integration. Ensure designs meet regulatory, architectural, and system-level requirements. Lead sustaining engineering, VAVE initiatives, and supplier transitions for existing and legacy products. Oversee root cause analysis and corrective actions for field and manufacturing issues. Guide the reverse engineering and redesign of legacy systems and components. Champion best practices in Analog, Digital, and Mixed-signal design. Support DfM/DfT, system verification, and V&V activities across the product life cycle. Ensure EMI/EMC compliance and integrate high-voltage and power supply modules (SMPS) into designs. Review and approve PCBA/electrical design specifications for release to manufacturing. Work closely with global and local teams across Systems Engineering, Software, Design Transfer, Quality, and Regulatory. Partner with external vendors, design houses, and contract manufacturers. Contribute to technology planning, roadmaps, and continuous improvement projects. You're the right fit if: Bachelor's/Master’s in electrical, Electronics, EE, Control systems, High voltage or equivalent. A master’s degree is preferred. Total 12+ years’ experience with a Minimum of 5+ years of People Management experience in a Class-3 medical device or other similar industry. Several years of hands-on experience in leading medical devices/products development/maintenance. Strong hands-on experience in Analog/digital/mixed-signal circuit design. Proficient in PCB design, schematic entry (Mentor Graphics or equivalent) Excellent communication skills and handling of stakeholder. Strong technical background in R&D engineering disciplines (e.g. FPGA/ Microprocessor/ DSP, PCBA design, High voltage electronics). Solid understanding of high-voltage design, SMPS, EMI/EMC standards, and board-level troubleshooting. Familiar with FDA 21 CFR Part 820.30, IEC 60601-1, ISO 13485, and CE/FDA compliance processes. Demonstrated ability to lead technical teams, manage stakeholders, and drive cross-functional execution. Strong mentoring, decision-making, and problem-solving capabilities. Experience with international medical Quality and Regulatory standards (e.g. IEC, FDA, UL, CE, etc.) is preferred. How We Work Together We believe that we are better together than apart. For our office-based teams, this means working in-person at least 3 days per week. Onsite roles require full-time presence in the company’s facilities. Field roles are most effectively done outside of the company’s main facilities, generally at the customers’ or suppliers’ locations. This role is an office-based role. About Philips We are a health technology company. We built our entire company around the belief that every human matters, and we won't stop until everybody everywhere has access to the quality healthcare that we all deserve. Do the work of your life to help the lives of others. Learn more about our business. Discover our rich and exciting history. Learn more about our purpose. If you’re interested in this role and have many, but not all, of the experiences needed, we encourage you to apply. You may still be the right candidate for this or other opportunities at Philips. Learn more about our culture of impact with care here.

Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy solutions for natural and built assets. We are more than 36,000 people, in over 70 countries, dedicated to improving quality of life. Everyone has an important role to play. With the power of many curious minds, together we can solve the world’s most complex challenges and deliver more impact together. Role description: We are now recruiting for an Assistant/Engineer with experience in transportation planning and modelling for our Mobility Advisory group in the GEC Bangalore office to support project delivery focusing on supporting project managers to deliver their project objectives and outcomes. Role accountabilities: Experience in transport modelling (e.g. highways, public transport, multimodal modelling, junction modelling). Knowledge and awareness in transport planning and strategy development (e.g., development planning, Transport Assessment, active travel) Experience of specification, delivery and application of strategic transport models. Proven ability to build, calibrate and validate traffic models with minimum supervision and experience in implementing demand models. Proven experience in PTV VISUM/VISSIM/CUBE/SATURN modelling suite. Experience with spreadsheet analysis and spreadsheet-based models. Knowledgeable user of data analytics and mapping tools (GIS) and able to interpret quantitative transport models. Ability to support the delivery of transport technical documents including Excel, GIS and Word skills, client letters/emails. Ability to work within a team / Working on your own initiative. Aptitude to learn and diversify skill base. Good communication skills. Good organisational skills. Mathematics and Statistic skills are all important. Strong problem solving and attention to detail. Ability to come up with practical solutions. Enthusiastic, Willing to learn, Punctual, Reliable, Committed. Qualifications & Experience: Degree qualified or equivalent essential (e.g. transport planning, civil engineering, geography, economics, mathematics or data science). Additional qualifications in a relevant discipline would be desirable. Working towards a professional qualification with a relevant professional institution (CIHT, ICE, RTPI) desirable. Nice to Have: Knowledge and understanding of Department for Transport’s Transport Appraisal Guidance (TAG). Experience of working with strategic transport clients such as National Highways, HS2, DfT, Welsh Government, Regional Transport Bodies for role 1 and for role 2 with developers, key clients such as Hs2, airports, local authorities etc. Experience in more than one Strategic modelling platform i.e, SATURN, EMME, CUBE, VISUM. Experience in Operational Modelling Platform i.e., VISSIM/SYNCHRO/LINSIG/AIMSUN Have an interest in developing digital skills such as data analysis or Python coding. Why Arcadis? We can only achieve our goals when everyone is empowered to be their best. We believe everyone's contribution matters. It’s why we are pioneering a skills-based approach, where you can harness your unique experience and expertise to carve your career path and maximize the impact we can make together. You’ll do meaningful work, and no matter what role, you’ll be helping to deliver sustainable solutions for a more prosperous planet. Make your mark, on your career, your colleagues, your clients, your life and the world around you. Together, we can create a lasting legacy. Join Arcadis. Create a Legacy. Our Commitment to Equality, Diversity, Inclusion & Belonging We want you to be able to bring your best self to work every day which is why equality and inclusion is at the forefront of all our activities. Our ambition is to be an employer of choice and provide a great place to work for all our people. We are an equal opportunity employer; women, minorities, and people with disabilities are strongly encouraged to apply. We are dedicated to a policy of non-discrimination in employment on any basis including race, caste, creed, colour, religion, sex, age, disability, marital status, sexual orientation, and gender identity. #JoinArcadis #CreateALegacy #Hybrid

Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy solutions for natural and built assets. We are more than 36,000 people, in over 70 countries, dedicated to improving quality of life. Everyone has an important role to play. With the power of many curious minds, together we can solve the world’s most complex challenges and deliver more impact together. Role Description: You will support a wide range of transport planning services, including but not limited to: Multimodal transport strategy development Future mobility planning (EVs, MaaS, alternative fuels) Business case and funding bid support Multimodal and junction modelling Pedestrian and active travel planning Feasibility studies and concept design Transport inputs to masterplanning and planning applications Behaviour change and sustainable travel strategies Local operational modelling and transport assessments Role Accountabilities: Experience in transport modelling (e.g. highways, public transport, multimodal) Knowledge of strategic model development and application Proficiency in tools such as VISUM, VISSIM, SATURN, CUBE or Experience with operational modelling (e.g. LINSIG, SYNCHRO, AIMSUN) Strong skills in data analysis, spreadsheet modelling, and GIS Ability to contribute to technical reports and client communication Good problem-solving, organisation, and communication skills A proactive, motivated approach with a willingness to learn and collaborate Nice to have : Familiarity with DfT’s Transport Appraisal Guidance (TAG) Exposure to working with public sector clients (e.g. HS2, National Highways, DfT) or developers Interest or experience in Python coding or data analysis Qualifications and Experience: Degree in a relevant field (e.g. Transport Planning, Civil Engineering, Geography, Economics, Mathematics, or Data Science) Working towards or interested in professional qualification (CIHT, ICE, RTPI) Why Arcadis? We can only achieve our goals when everyone is empowered to be their best. We believe everyone's contribution matters. It’s why we are pioneering a skills-based approach, where you can harness your unique experience and expertise to carve your career path and maximize the impact we can make together. You’ll do meaningful work, and no matter what role, you’ll be helping to deliver sustainable solutions for a more prosperous planet. Make your mark, on your career, your colleagues, your clients, your life and the world around you. Together, we can create a lasting legacy. Join Arcadis. Create a Legacy. Our Commitment to Equality, Diversity, Inclusion & Belonging We want you to be able to bring your best self to work every day which is why equality and inclusion is at the forefront of all our activities. Our ambition is to be an employer of choice and provide a great place to work for all our people. We are an equal opportunity employer; women, minorities, and people with disabilities are strongly encouraged to apply. We are dedicated to a policy of non-discrimination in employment on any basis including race, caste, creed, colour, religion, sex, age, disability, marital status, sexual orientation, and gender identity. #JoinArcadis #CreateALegacy #Hybrid

Job ID: 32015 Location: Chennai, IN Area of interest: Technology Job type: Regular Employee Work style: Office Working Opening date: 4 Jul 2025 Job Summary Understand requirement, prepare and execute tests and adhere to all test controls Good experience in Integration Testing, System Testing, API Testing. Automate functional test cases They will ensure that teams can validate the quality of the product delivered to the stakeholders as per group standards. Works within scrum and reports to Test manager Must have technical skills Understand BDD and functional test automation Have demonstrable programming knowledge in one OOP language, preferably Java Ability to coach, and guide junior test engineers Full understanding of the SDCLC especially Agile methodologies Familiar with test management process ISTQB or Agile Test Certified Banking domain knowledge is a plus Understanding of continuous integration and deployment processes, or have the desire to learn Key Responsibilities Strategy Identify and analyse issues in requirements, design specifications, application architecture as well as product documentation. Develop test specifications based on various requirement documents within schedule constraints. Develop test bed and/or test data and verify test environments (based on project requirements). Develop regression packs to ensure that requirements from previous scope are still functioning as before. Perform functional and technical test execution activities (automated testing, where applicable) as per project engagement. Identify and is familiar with negative testing, to be included in the developed test specifications. Report and update test status promptly and accurately. Conduct reviews and inspections of project deliverables (for small size projects). Able to contribute to multiple projects, whilst still ensuring process compliance and deliverables are adhere to. Able to work independently as well as a team in providing out-of-the box solution if required. Business Constant communication and follow up with various stakeholders during test planning and execution phases. Enable project meetings to provide feedback and statistics of the project in relation to the test quality. Processes Good understanding and able to apply test processes laid down within the test team, and/or standards as defined by project and SCB. Understand that traceability and reporting are extremely important in highly compliant environments and be prepared to engrain these practices in team’s ways of working People & Talent Ability to work in a highly compliant landscape and work within the boundaries of globally defined software quality management practices and policies Able to work independently in scrum team as a tester, but maintain good collaboration with other team members and stake holders. Risk Management To collaborate/troubleshoot with the development and delivery team for technical issues that requires result analysis and feedback. Raise any concerns at the right time to Test manager and delivery manager Governance Effectively and collaboratively identify, escalate, mitigate and resolve risk, conduct and compliance matters. Regulatory & Business Conduct Display exemplary conduct and live by the Group’s Values and Code of Conduct. Take personal responsibility for embedding the highest standards of ethics, including regulatory and business conduct, across Standard Chartered Bank. This includes understanding and ensuring compliance with, in letter and spirit, all applicable laws, regulations, guidelines and the Group Code of Conduct. Key stakeholders Engineering leads (Scrum master), Test manager Our Ideal Candidate Functional testing Automation testing selenium and cucumber Test management SDLC process Agile team work Competencies Action Oriented Collaborates Customer Focus Gives Clarity & Guidance Manages Ambiguity Develops Talent Drives Vision & Purpose Nimble Learning Decision Quality Courage Instills Trust Strategic Mindset Technical Competencies: This is a generic competency to evaluate candidate on role-specific technical skills and requirements About Standard Chartered We're an international bank, nimble enough to act, big enough for impact. For more than 170 years, we've worked to make a positive difference for our clients, communities, and each other. We question the status quo, love a challenge and enjoy finding new opportunities to grow and do better than before. If you're looking for a career with purpose and you want to work for a bank making a difference, we want to hear from you. You can count on us to celebrate your unique talents and we can't wait to see the talents you can bring us. Our purpose, to drive commerce and prosperity through our unique diversity, together with our brand promise, to be here for good are achieved by how we each live our valued behaviours. When you work with us, you'll see how we value difference and advocate inclusion. Together we: Do the right thing and are assertive, challenge one another, and live with integrity, while putting the client at the heart of what we do Never settle, continuously striving to improve and innovate, keeping things simple and learning from doing well, and not so well Are better together, we can be ourselves, be inclusive, see more good in others, and work collectively to build for the long term What we offer In line with our Fair Pay Charter, we offer a competitive salary and benefits to support your mental, physical, financial and social wellbeing. Core bank funding for retirement savings, medical and life insurance, with flexible and voluntary benefits available in some locations. Time-off including annual leave, parental/maternity (20 weeks), sabbatical (12 months maximum) and volunteering leave (3 days), along with minimum global standards for annual and public holiday, which is combined to 30 days minimum. Flexible working options based around home and office locations, with flexible working patterns. Proactive wellbeing support through Unmind, a market-leading digital wellbeing platform, development courses for resilience and other human skills, global Employee Assistance Programme, sick leave, mental health first-aiders and all sorts of self-help toolkits A continuous learning culture to support your growth, with opportunities to reskill and upskill and access to physical, virtual and digital learning. Being part of an inclusive and values driven organisation, one that embraces and celebrates our unique diversity, across our teams, business functions and geographies - everyone feels respected and can realise their full potential. Recruitment Assessments Some of our roles use assessments to help us understand how suitable you are for the role you've applied to. If you are invited to take an assessment, this is great news. It means your application has progressed to an important stage of our recruitment process. Visit our careers website www.sc.com/careers www.sc.com/careers

Role Summary: This is a technical leadership position responsible for building and leading our computational research capabilities from the ground up. The role combines deep technical expertise in battery modelling with team leadership and strategic thinking to create a multi-scale simulation platform that will transform how the company designs and optimises battery technology. Success in this position looks like: Successfully architecting and deploying a comprehensive modelling platform that integrates quantum to manufacturing-scale simulations, building and mentoring a high-performing team of 3-5 researchers, reducing R&D development cycles by 10x through predictive design capabilities, and establishing validated computational workflows that directly inform production decisions. Organisational fit: This role reports directly to the CTO and serves as the technical foundation for our data-driven approach to battery innovation. The position bridges the gap between fundamental research and manufacturing optimisation, making it central to the company's mission of revolutionising battery technology through computational innovation. Responsibilities: Architect and design a multi-scale simulation framework that seamlessly integrates quantum mechanics (DFT), molecular dynamics, mesoscale, and continuum models using modern integration protocols Build, hire, and mentor a world-class computational battery research team of 3-5 scientists, establishing technical standards and fostering innovation Develop comprehensive physics-based models for battery degradation mechanisms including SEI formation, lithium plating, and thermal effects Create robust APIs and integration interfaces connecting simulation platforms with experimental data collection systems Establish and validate computational predictions through systematic comparison with experimental data from manufacturing facilities Drive breakthrough research by coupling plasma deposition physics with electrochemical modelling for novel material discovery Transform organisational R&D methodology from trial-and-error approaches to predictive design workflows Qualifications: Education: Masters in Computational Materials Science, Chemical Engineering, or Physics, or Master's degree with 5+ years of relevant industry experience Technical Expertise: Proven experience in battery modeling including electrochemistry, transport phenomena, and degradation mechanisms Software Proficiency: Hands-on experience with at least two of the following: COMSOL Multiphysics, LAMMPS, VASP, or Quantum ESPRESSO Programming Skills: Strong Python programming capabilities and scientific computing experience Systems Experience: Demonstrated track record of building and deploying production-scale simulation systems Leadership Experience: Experience managing technical teams or leading complex multi-stakeholder projects Preferred Qualifications: Knowledge of plasma physics and surface chemistry, experience with Model Context Protocol (MCP) or similar integration frameworks, machine learning experience for surrogate model development, published research in battery simulation or computational electrochemistry, and startup or high-growth environment experience Communication Skills: Ability to present complex technical concepts to diverse stakeholders and collaborate effectively across interdisciplinary teams

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Lattice Semiconductor is seeking a Sr. Staff Physical Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role Specifics This is a full-time individual contributor position located in Pune, India. The qualified candidate will be implementing and lead RTL to GDSII flow for complex design. The qualified candidate will work and lead one or more aspects of physical design including place & route, CTS, routing, floorplanning, powerplanning, timing and physical signoff The qualified candidate is expected to have experience in physical design signoff checks, including timing closure, EM/RV and physical verification (DRC, LVS). The qualified candidate is expected to drive efficiency and quality of physical design flow and methodology and work together with internal EDA team and external tool vendors The qualified candidate is expected to have scripting knowledge or perl /python etc to improve design efficiency and methodology development. Collaborate with RTL, DFT , verification and full chip teams to ensure robust design implementation. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student. Accountabilities Serve as a key contributor to FPGA design efforts. Drive physical design closure of key ASIC blocks & full chip and bring best-in-class methodologies to achieve best power, performance, and area. Ensuring design quality through all physical design quality checks and signoff. Develop strong relationships with worldwide teams. Mentor and develop strong partners and colleagues. Occasional travel as needed. Required Skills BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 12+ years of experience in driving physical design activities of ASIC blocks and full chip. Must have experience of multiple tapeouts Experience on working with industry standard physical design tools including Innovus, Genus, Tempus, voltus, calibre, conformal etc. Independent worker with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

About the Role — PCB Design Engineer Location: Gurugram Experience: 5–10 Years Qualification: B.Tech/B.E. in Electrical/Electronics/ECE or related discipline (Mandatory) Who We Are: At Boon , we’re building cutting-edge water tech solutions to make clean drinking water more sustainable, efficient, and accessible. As part of our Power Electronics team, you’ll help us develop high-performance hardware that powers next-generation water purification and distribution systems deployed globally. Role Overview: We’re looking for an experienced PCB Design Engineer with deep expertise in designing robust, high-reliability PCBs for power electronics applications. You’ll work extensively with Altium and other tools , apply EMI/EMC best practices, and handle thermal-critical layouts for power-dense systems. Key Responsibilities: Design complex, multi-layer PCBs for power electronics including DC-DC converters, inverters, SMPS, and motor drives. Develop and maintain schematic diagrams, PCB layouts, footprints, and libraries in Altium Designer. Optimize PCB layouts for signal integrity, power integrity, thermal performance, and high-current handling. Ensure compliance with EMI/EMC standards and integrate grounding, shielding, and filtering best practices. Perform DRC/ERC checks and support DFM/DFT processes for manufacturability and testability. Collaborate cross-functionally with electrical, mechanical, and firmware engineers throughout product development. Integrate 3D component models and conduct mechanical fit and clearance checks using Altium’s 3D design capabilities. Coordinate with PCB fabrication and assembly vendors for prototyping and production runs. Support prototype bring-up, debugging, and validation with the testing team. Manage documentation including Gerber files, BOMs, assembly drawings, and design revisions. What You’ll Need: Bachelor’s degree in Electronics/Electrical Engineering or a related field. 7–10 years of hands-on PCB design experience, ideally in power electronics. Advanced proficiency with Altium Designer (schematic, layout, 3D, library management). Strong understanding of EMI/EMC principles and practical implementation. Experience designing for high-voltage, high-current, and thermally demanding applications. Competency in 3D modeling and mechanical integration of PCB assemblies. Solid grasp of IPC standards and PCB manufacturing processes. Excellent analytical, problem-solving, and debugging skills. Strong communication and teamwork abilities. Join us at Boon and help shape innovative hardware that makes clean water more sustainable for millions.

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

About Company Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. We’re Hiring – DFT (Design for Test) Engineer Locations: Bangalore | Hyderabad | Cochin | Pune Experience: 7 to 12 Years Qualification: Bachelor’s in Computer Science / Electronics / Electrical Engineering Key Responsibilities Collaborate with ASIC design teams to ensure DFT rules and coverage are met Generate high-quality ATPG patterns for SAF/TDF using on-chip test compression Work on MBIST verification and repair using tools like Mentor Run ATPG & MBIST verification using unit delay and min/max corner simulations Deliver manufacturing test patterns for ATE in collaboration with product/test teams Support post-silicon debug and issue resolution Develop diagnostic tools for ATPG, MBIST, and ATE bring-up Enhance and maintain scripting for DFT flows Preferred Experience & Skills Hands-on experience with Full Chip DFT and Silicon Validation Strong understanding of DFT concepts, ATPG coverage, yield enhancement, and silicon debug Proficient in Memory test & failure analysis Tool knowledge: ATPG – TestKompress MBIST – MentorETVerify Simulation – VCS (preferred), ModelSim Scripting in Perl, Shell is a plus Comfortable working in international teams with strong communication skills Ability to multitask and work on high-priority designs in parallel Quick learner, adaptable to new tools and methodologies Qualifications Bachelor’s degree in Computer Science, Electronics, or Electrical Engineering Minimum of 7 years of relevant experience in DFT Strong analytical and troubleshooting skills Ability to work independently and as part of a team Excellent verbal and written communication skills Experience with industry-standard tools and methodologies Benefits and Perks Competitive Salary Good work culture Skills: memory test,dft,failure analysis,atpg,communication,scripting,silicon validation,mbist