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Job Description:
The staff FPGA/SoC integration engineer will be responsible for integrating all custom and external IP’s into the FPGA top. This high visibility role involves ownership of chip top RTL, place/route and timing closure and other deliverables needed to release the FPGA for production.
Duties & Responsibilities
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Develop flows and methodologies that improves on current methodology to integrate complex IP’s into FPGA chip-top using digital-on-top (DoT) approach.
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Develop tools and scripts (RTL and custom scripts) to verify connectivity and functionality of chip-top.
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Own chip level floorplan activities, place and route, timing closure, and physical and electrical verification.
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Coordinate activities between different groups like architecture, design, software and verification to ensure smooth integration of various IP’s into the chip top.
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Generate netlists with different views for software, physical, electrical and functional verification.
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Collaborate with the packaging team to generate package files for several different members of the FPGA product family.
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Work with verification team to help debug chip top level integration issues related to timing and functionality.
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Effectively presenting technical information to small teams of engineers.
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Communicate regularly with the management, design and verification teams in multiple locations to resolve issues, update status and solve technical problems related to chip/SoC integration and delivery.
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Become well-versed in new ASIC and custom tools related to chip integration.
Requirements/Qualifications:
Experience Required
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Minimum of 15years of proven silicon design experience in ASIC design flow including RTL design, implementation, functional validation.
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Extensive knowledge of integration of several complex custom and ASIC IP’s at chip-top level using DoT(digital on top) methodology.
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Expert in ASIC flow and methodology.
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Experience with System Verilog/Verilog, synthesis, STA and place and route is required.
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Expert in usage of ASIC tools like Innovus, Tempus, Magillem, Verdi or similar is required.
Other Requirements
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Demonstrated competency in scripting, managing simulation queues, and data capture plus presentation using Microsoft Office tools, including Excel.
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Ability to support layout, verification, timing characterization, and software model developers.
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Good analytical, oral and written communication skills
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Able to write clean, readable presentations.
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Self-motivated, proactive team player.
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Ability to work to schedule requirements.
Beneficial Experience
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Experience in ASIC development, several technology nodes.
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Experience with verification methodologies such as SystemVerilog/UVM.
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Experience in low power design.
Qualification:
Bachelors or Master’s in Electrical Engineering, Physics, Computer Engineering or Computer Science preferred.
Travel Time:
No Travel
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
