Senior Engineer II-Design For Test

Job Description

Are you looking for a unique opportunity to be a part of something greatWant to join a 20,000-member team that works on the technology that powers the world around usLooking for an atmosphere of trust, empowerment, respect, diversity, and communicationHow about an opportunity to own a piece of a multi-billion dollar (with a B!) global organizationWe offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: Microchip AES Design team in Bangalore is looking for an experienced and motivated Design-For-Test Senior Engineer to provide test hardware solution for various microchip B usiness units. As a member of test development team, you will be responsible for understanding the existing DFT test structures and clock strategy used across multiple business units and provide architectural improvements to improve test coverage . The candidate should have experience with ATPG and MBIST. The candidate should have in depth knowledge of Tessent /Modus tool execution. Requirements/Qualifications: Qualified applicants will possess the following skills / experience: Hands on expertise on handling DFT on hierarchical designs. Hands on expertise on Tessent /Modus ATPG tool for DFT setup and pattern generations. Hands on expertise on Tessent /Modus MBIST tool for MBIST hardware generation. Hands on expertise on Tessent /Modus diagnosis tool for on-silicon debug. Hands on expertise SCAN pattern simulations and debug. ATPG with the pattern delivery to the test engineering team . Sound knowledge of Scan Stitching, Scan Compression, MBIST JTAG Techniques . Should have good post silicon DFT bring-up and debug experience . Should have a good knowledge in simulation debug and prior experience at SoC level . Excellent written and verbal communication skills. Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals. Experience: Bachelors/Masters in Electronics or equivalent degree with 7 + years of experience Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.