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Capgemini
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Rtl Design Engineer

Rtl Design Engineer

Capgemini

3 - 7 years

4 - 9 Lacs

bengaluru

Posted:5 days ago| Platform:

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Skills Required

perl synthesis python verilog lint usb soc lpddr vhdl microservices apb rtl design axi fpga rtl coding shell scripting ahb i2c tcl system verilog arm sta asic cdc ip rtl spi uvm cadence ethernet ddr uart spyglass dma pcie soc integration dc

Work Mode

Work from Office

Job Type

Full Time

Job Description

About The Role
About The Role
Should be good in Integration of SOC & RTL coding.
Should be aware of SOC flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.
Should have good understanding of SoC flows. Primary
Skills:

VHDL, Verilog,Micro-architecture, R TL coding,CDC, Lint, Synthesis, STA,IP development , SoC integration,VCLP,scripting -Perl,Python,Shell, and Tcl.
Secondary
Skills:

Synopsis/Cadence tool flow,ARM Coretex,DMA, DDR, SPI, I2C, UART,AHB/AXI/APB,Ethernet, USB, PCIe,Mipi CSI/DSI, LPDDR. Education
B.E/B.Tech/ Any Engineering.

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Rtl Design Engineer