Job Summary: We are looking for a skilled and motivated Formal Verification Engineer to join our growing team. The ideal candidate will have a strong background in formal methods, digital design, and verification for complex SoC/CPU/GPU designs. This role involves working closely with design and DV teams to ensure bug-free, high-quality silicon. Key Responsibilities: Develop and execute formal verification test plans for complex digital blocks. Write assertions using SVA or PSL to capture design intent. Apply formal techniques to identify design issues and verify functional correctness. Work with RTL designers and functional DV teams to debug and close verification gaps. Use industry-standard formal verification tools (e.g., Jasper Gold, VC Formal). Required Skills: Minimum 3 years of experience in digital design or verification. Strong grasp of VLSI concepts, FSMs, and RTL design. Hands-on experience with formal verification methodologies. Proficient in assertion-based verification (SVA/PSL). Familiarity with EDA tools (Synopsys, Cadence). Good scripting skills in Python, Perl, or TCL. Preferred Qualifications: Experience in SoC/CPU/GPU or cellular design verification. Exposure to industry-standard protocols (AXI, AHB, etc.). Strong debugging and problem-solving skills. Education: B.E./B. Tech or M.E./M. Tech in ECE, EE, or a related field.
Job Description RTL Design & Static Verification Engineer (4+ years) Seeking an experienced RTL Design and Verification Engineer with strong expertise in static verification methodologies for SoC signoff. The ideal candidate should possess hands-on experience with RTL design, Lint/CDC/RDC analysis, and UPF-based power-aware verification. Proficiency in SystemVerilog, Verilog, and Python is essential, along with familiarity with tools like Spyglass, Meridian, and Ascent. The role involves flow automation, cross-functional collaboration with design and power teams, and driving methodology enhancements from specification to deployment. Roles and Responsibilities Develop, analyze, and optimize RTL designs for complex SoC architectures. Perform static verification (Lint, CDC, RDC, DFT, Low Power) for RTL and netlist signoff. Implement UPF-based power-aware verification to validate power domain connectivity and glitch detection. Drive methodology enhancements and define new static rule checks in collaboration with R&D teams. Automate verification flows using Python/CShell to improve efficiency and debug turnaround time. Collaborate with design, verification, and power teams to ensure seamless SoC integration. Support customer PoCs and enable cross-functional adoption of new verification methodologies