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Metavlsi Technologies
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Formal Verification

Formal Verification

Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

Metavlsi Technologies

3 - 7 years

0 Lacs

bengaluru

Posted:2 weeks ago| Platform:

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Skills Required

fpv sv connectivity uvm

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Job Type

Full Time

Job Description

Job Summary:

We are looking for a skilled and motivated Formal Verification Engineer to join our growing team. The ideal candidate will have a strong background in formal methods, digital design, and verification for complex SoC/CPU/GPU designs. This role involves working closely with design and DV teams to ensure bug-free, high-quality silicon.

Key Responsibilities:

Develop and execute formal verification test plans for complex digital blocks.
Write assertions using SVA or PSL to capture design intent.
Apply formal techniques to identify design issues and verify functional correctness.
Work with RTL designers and functional DV teams to debug and close verification gaps.
Use industry-standard formal verification tools (e.g., Jasper Gold, VC Formal).

Required Skills:

Minimum 3 years of experience in digital design or verification.
Strong grasp of VLSI concepts, FSMs, and RTL design.
Hands-on experience with formal verification methodologies.
Proficient in assertion-based verification (SVA/PSL).
Familiarity with EDA tools (Synopsys, Cadence).
Good scripting skills in Python, Perl, or TCL.

Preferred Qualifications:

Experience in SoC/CPU/GPU or cellular design verification.
Exposure to industry-standard protocols (AXI, AHB, etc.).
Strong debugging and problem-solving skills.

Education:

B.E./B. Tech or M.E./M. Tech in ECE, EE, or a related field.

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