Posted:9 hours ago|
Platform:
Work from Office
Full Time
Requirements:
Bachelors or Master’s degree in Electrical Engineering.
Minimum of 4-7 years of experience in digital RTL design.
Proficiency in Verilog, and System Verilog.
Experience with industry-standard design tools such as Cadence, Synopsys.
Strong understanding of digital design principles and RTL coding.
Excellent problem-solving and debugging skills.
Experience in clock domain crossing (CDC) and reset domain crossing (RDC).
Knowledge of scripting languages (e.g., Python, Perl) is a plus.
Object Technology Solutions
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