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EDA Methodology Engineer ASIC Formality

EDA Methodology Engineer ASIC Formality

IBM

8 - 13 years

10 - 14 Lacs

bengaluru

Posted:2 days ago| Platform:

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Skills Required

vhdl rtl design system verilog tcl verilog physical design c++ soc design verification formal verification fpga soc design rtl coding perl synthesis asic sta python eda cdc rtl timing analysis uvm asic design lint timing closure vlsi synopsys

Work Mode

Work from Office

Job Type

Full Time

Job Description

Develop and maintain formal equivalence checking flows using Synopsys Formality.

Collaborate with cross-functional teams to align verification methodology with design goals.

Implement and support Formality ECO flows for incremental synthesis.

Drive methodology improvements for SoC design verification.

Coordinate with internal stakeholders and external vendors to deliver high-quality solutions.

Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise

Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSI Design.

5–8 years of hands-on experience with Synopsys Formality or similar tools (e.g., Cadence Conformal LEC,JasperGold).

Strong understanding of RTL design languagesVHDL, Verilog,SystemVerilog.

ExpertiseinTcland Python scripting.

Deep knowledge of logic synthesis and gate-level netlist verification.

Experience in setting up and running equivalence checks between RTL and synthesized netlists.

Proven ability to troubleshoot and resolve complex verification issues.

Strong communicationand collaboration skills.

Preferred technical and professional experience

Experience with Formality ECO flows.

Familiarity with formal verification methodologies in large-scale SoC projects.

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