Senior Lead

Tessolve

4 years

0 Lacs

bengaluru karnataka india

Posted:8 hours ago| Platform:

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Skills Required

design electrical compiler timing strategies scripting power analysis flow synthesis routing planning resolve electromigration signal integrity drc lvs checks cad verification drive optimization constraints support test dft documentation

Work Mode

On-site

Job Type

Full Time

Job Description

ob Title:

Experience:

Location:

Employment Type:

Required Qualifications

Bachelor’s or Master’s degree in
Electronics/Electrical/Computer Engineering
or related field.
4+ years
of hands‑on experience in ASIC/SoC
Physical Design
.
Strong understanding of physical design flows (RTL2GDSII).
Experience with EDA tools such as
Synopsys
,
Cadence
,
Mentor
– e.g., IC Compiler, Innovus, PrimeTime, Tempus, Hercules, etc.
Proficiency in STA, timing closure techniques, clocking strategies, congestion analysis.
Good scripting skills in
Tcl
,
Perl
,
Python
, or
Shell
.
Knowledge of power analysis, floorplanning, ECO flow, clock tree synthesis, and routing optimization

Key Responsibilities

Execute physical design implementation flow from RTL to GDSII for complex SoC/ASIC projects.
Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
Conduct timing closure using STA tools and methodologies, including multi‑corner/multi‑mode analysis (MCMM).
Resolve congestion, IR drop, electromigration (EM), and signal integrity challenges.
Perform DRC/LVS/ERC checks and collaborate with CAD team for ECO and fix strategies.
Work closely with RTL, synthesis, verification, and backend teams to ensure successful tape‑out.
Drive performance, area, power (PPA) optimization based on constraints and design goals.
Develop and maintain RTL constraints, SDC, and scripts for design implementation.
Support design for test (DFT) insertion and validation.
Provide design documentation and participate in design reviews.

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