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Smart Soc Solutions
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RTL DESIGN LEAD ENGINEER

RTL DESIGN LEAD ENGINEER

Smart Soc Solutions

8 - 13 years

8 - 12 Lacs

Hyderabad Bengaluru

Posted:1 week ago| Platform:

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Skills Required

bus ahb cdc lint infrastructure c++ soc device drivers vhdl rtl design arm cortex rtos axi fpga linux rtl coding i2c perl system verilog synthesis asic sta c ip rtl timing analysis spi uvm verilog asic design silicon uart vlsi soc integration

Work Mode

Work from Office

Job Type

Full Time

Job Description

RTL DESIGN LEAD ENGINEERThe ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. The job will involve RTL design, front-end tools flow, and SoC integration/porting-related tasks. Desired Skills and Experience-

8+ years of Experience

Engineering experience with exposure to front end ASIC tool flows

Should be self-driven and independent in tracking and closing tasks with respective holders.

In depth knowledge of AHB and bus infrastructures like matrix and fabrics

Good understanding of ARM based SoC Architecture

Exposure to ARM Cortex A/M integration or support

Good understanding of SoC DV methodology

Good experience in Low-Power design methodology

Hands-on experience with ASIC tools Lint, CDC etc

System Verilog/Verilog RTL coding Power aware RTL coding/design knowledge

Understanding of Clock-Structures/Scheme Good Communication Skills

Job Category VLSI (Silicon engineering)
Job Location IndiaBangalore IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USATexas

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RTL DESIGN LEAD ENGINEER