86 Bus Jobs

: Paytm Travel is on a mission to be the most trusted and customer-centric travel platform in India. We’re already among the top 3 players in the bus ticketing space and are rapidly expanding our partner ecosystem across states. We're looking for a high-energy, data-driven professional to lead our regional supply partnerships and shape the next phase of growth. Role Overview: As the Regional Lead, you will be responsible for managing and growing Paytm’s relationships with State Road Transport Corporations (RTCs) and private bus operators in your assigned region. You will drive strategic partnerships, ensure competitive supply availability, and take end-to-end ownership of regional revenue, pricing health, and operational performance. Key Responsibilities: Partnership & Supply Management Build, maintain, and expand strong working relationships with RTCs and top private operators in the region. Onboard new operators and ensure digital adoption of Paytm Travel tools and dashboards. Negotiate commission structures, payout terms, and commercial agreements aligned with platform objectives. Revenue & Performance Management Own and drive revenue targets, load factors, and seat fill rates for your region. Collaborate with central pricing and analytics teams to implement dynamic pricing strategies. Track revenue leakage, cancellations, and penal charges; work with operators to resolve issues. Market & Competition Analysis Regularly benchmark fares, seat inventory, and operator quality against regional competitors. Provide actionable insights on price trends, route-level demand patterns, and consumer behavior. Recommend product/UX changes based on feedback from operators and market observations. Operational Excellence Monitor SLA adherence on seat confirmations, refunds, and cancellation handling. Collaborate with customer support and tech teams to address escalations and resolve partner issues. Run regular health checks and audits on partner performance and NPS metrics. What We're Looking For: 5–10 years of experience in bus ticketing, logistics, e-commerce, or B2B travel partnerships Prior experience working with state transport corporations or regional aggregators is a strong plus Strong commercial acumen with negotiation experience Data-savvyComfortable working with dashboards, Excel, and BI tools to derive insights Deep understanding of regional travel patterns, fares, and operational intricacies Excellent communication skills in English and the local regional language Willingness to travel extensively across the assigned territory Why join us 1. A collaborative output-driven program that brings cohesiveness across businesses through technology 2. Improve the average revenue per use by increasing the cross-sell opportunities 3. A solid 360 feedback from your peer teams on your support of their goals 4. Respect, that is earned, not demanded from your peers and manager Compensation: If you are the right fit, we believe in creating wealth for you With enviable 500 mn+ registered users, 21 mn+ merchants and depth of data in our ecosystem, we are in a unique position to democratize credit for deserving consumers & merchants – and we are committed to it. India’s largest digital lending story is brewing here. It’s your opportunity to be a part of the story!

Project Role : Business Process Architect Project Role Description : Analyze and design new business processes to create the documentation that guides the implementation of new processes and technologies. Partner with the business to define product requirements and use cases to meet process and functional requirements. Participate in user and task analysis to represent business needs. Must have skills : SAP CO Management Accounting Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Business Process Architect, you will analyze and design new business processes to create documentation that guides the implementation of new processes and technologies. Your typical day will involve collaborating with various stakeholders to understand their needs, defining product requirements, and ensuring that the solutions developed align with the overall business objectives. You will engage in user and task analysis, translating business needs into actionable insights that drive process improvements and enhance operational efficiency. Roles & Responsibilities:- Expected to be an SME.- Collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Facilitate workshops and meetings to gather requirements and feedback from stakeholders.- Develop and maintain comprehensive documentation of business processes and system functionalities. Professional & Technical Skills: - Must To Have Skills: Proficiency in SAP CO Management Accounting.- Good To Have Skills: Experience with process mapping and modeling tools.- Strong analytical skills to assess business processes and identify areas for improvement.- Ability to communicate complex concepts clearly to diverse audiences.- Experience in project management methodologies to ensure timely delivery of solutions. Additional Information:- The candidate should have minimum 5 years of experience in SAP CO Management Accounting.- This position is based at our Mumbai office.- A 15 years full time education is required. Qualification 15 years full time education

Incumbent should be from an Engineering industry into Steel Fabrication & Industrial Racking production with minimum 2-5 years of experience and would be responsible for Production output, Safety, Discipline, Attendance, Absenteeism and Total Shift activity Job Responsibilities Handling of dedicated production activities/sub contract activities. Providing daily production. Plate cutting knowledge, bus body fabrication, and industrial racking fabrication will be preferred. Responsible for handling the complete shift operations and managing the workmen. Ensure the total loading operations carried out as per plan in a shift. Meeting the target of shipment as per the priorities set from time to time by monitoring the activities of checkers and operators. Verifying and confirming the shipper details while vehicles are being loaded in a shift. Monitoring the attendance of workmen in the shift and work allotment as per plan Strictly follow the priority (Jobs or Part marks) while loading Verifying the jobs before loading Ensuring the phase wise closing of the jobs as planned Should leave the work spot only after reliever takes the charge Educating the operators and chakkars towards priority items Candidate Requirements Age Range: 24-30 years 2-5 years in managing the workforce in manufacturing / engineering industry Supervisory skills Understanding the priority requirements Should be able to meet the targets set from time to time Manage the workmen and educate them with the requirements of job Go-getter, good at communication, influencing and convincing skills, good at People Management Education Diploma Bachelor s Degree

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM, System Verilog coding Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Communication and collaboration skills to work with a large world-wide design organization Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Proficiency in any of the Scripting languages (Python or Perl) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Join Qualcomms cutting-edge hardware engineering team to drive the design verification of next-generation SoCs, with a focus on wireless technologies including WLAN (IEEE 802.11). You will work on IP and subsystem-level verification, collaborating with cross-functional teams to deliver high-performance, low-power silicon solutions. A strong understanding of on-chip buses and bridges is essential to ensure seamless integration and performance across subsystems. Key Responsibilities Develop and execute verification plans for complex SoC designs and IP blocks. Architect and implement testbenches using SystemVerilog and UVM/OVM methodologies. Perform RTL verification, simulation, and debugging. Collaborate with design, architecture, and software teams to ensure functional correctness. Contribute to IP design reviews and sign-off processes. Support post-silicon validation and bring-up activities. Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance. Conduct CPU subsystem verification including coherency, cache behavior, and interrupt handling. Perform power-aware verification using UPF/CPF and validate low-power design intent. Execute performance verification to ensure bandwidth, latency, and throughput targets are met. Preferred Skills & Experience 2"“15 years of experience in digital design and verification. Deep understanding of bus protocols and bridge logic, including hands-on experience with AXI, AHB, and APB. Experience with CPU subsystem verification and performance modeling. Familiarity with wireless protocols (IEEE 802.11 a/b/g/n/ac/ax/be) is a plus. Proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python). Experience with power-aware verification methodologies and tools (e.g., UPF, CPF). Familiarity with performance verification techniques and metrics. Exposure to tools like Clearcase/Perforce and simulation/debug environments. Strong analytical, debugging, and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications Bachelors or Masters degree in Electrical/Electronics Engineering, Computer Science, or related field. Relevant experience in hardware design and verification.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Join Qualcomms Wireless IP team to design and develop cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. You will work on high-performance, low-power digital designs across the full VLSI development cycle"”from architecture and micro-architecture to RTL implementation and SoC integration. This role offers the opportunity to collaborate with global teams and contribute to market-leading wireless solutions. Key Responsibilities Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design convergence. Collaborate with system architects, verification, SoC, software, DFT, and physical design teams. Apply low-power design techniques including clock gating, power gating, and multi-voltage domains. Analyze and optimize for performance, area, and power. Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. Conduct CDC and lint checks using tools like Spyglass and resolve waivers. Participate in post-silicon debug and bring-up activities. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Skills & Experience 2"“15 years of experience in digital front-end ASIC/RTL design. Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable. Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. Experience with wireless modem IPs or similar high-performance digital blocks is a plus. Familiarity with low-power design methodologies and CDC handling. Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. Exposure to post-silicon debug and SoC integration challenges. Strong documentation and communication skills. Self-motivated with a collaborative mindset and ability to work with minimal supervision. Minimum Qualifications Bachelors or Masters degree in Electronics, VLSI, Communications, or related field. Proven experience in RTL design and SoC development.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of our highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle. Preferred qualifications B.E/B.Tech/M.E/M.Tech in Electronics with 5+ year experience in verification domain. Strong fundamentals in digital ASIC verification Experience in IP/SS/SoC level verification of medium to high complexity design Familiarity with system level HW and SW Debug techniques and Verification requirements A good understanding of the complete verification life cycle (test plan, testbench through coverage closure) Strong System Verilog/UVM based verification skills & Experience with Assertion & coverage-based verification methodology Experience w/ PSS or higher-level test construction languages is an added advantage Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc. Knowledge of one or more of Multimedia design blocks such as Display/Camera/Video/GFx Knowledge of one or more of peripheral blocks verification such as PCIe/USB/UFS/I3C Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Roles and Responsibilities Define verification architecture, develop test plans and build verification environment Work with design team to understand design intent and bring up verification plans and schedules Verify Subsystems and Full SoC using advanced verification methodologies Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard Develop test plan to verify all low power aspects across all modes of verification- RTL, PA-RTL, PA-GLS and Formal Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Assist in silicon bring-up, debug and bring-up activities Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Overview: Person will be responsible for developing next generation SoCs for mobile products and its adjacencies. The role will require the candidate to understand and work on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. The person is also responsible for overseeing physical design and verification aspects. : - Full chip design for multi million gates SoC- Digital design and development (RTL)- Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification- Manage IP dependencies, planning and tracking of all front end design related tasks- Driving the project milestones across the design, verification and physical implementations Minimum Qualifications: - Minimum 15 years of solid experience SoC design- Developing architecture and micro-architecture from specs- Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC- Understanding of Memory controller designs and Microprocessors is an added advantage- Understanding of Chip IO design and packaging is an added advantage- Familiarity with various bus protocols like AHB, AXI is highly desired- Ability to review top level test plans- Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC- Working knowledge of timing closure is a must - Should have good post silicon bring up and debug experience - Should have good SoC integration exposure and its challenges - Should have good exposure to design verification aspects - Having SoC specification to GDS to commercialization experience is highly desired - Needs to makes effective and timely decisions, even with incomplete information.- Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas.- Provides direction, mentoring, and leadership to a small to medium sized groups.- Should possess strong communication and leadership skills to ensure effective communication with Program

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM, System Verilog coding Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Communication and collaboration skills to work with a large world-wide design organization Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Proficiency in any of the Scripting languages (Python or Perl)

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Would be working on Qualcomm Snapdragon CPUSS Architecture and performance team. Responsible for analyzing the performance aspects of Snapdragon CPU subsystem and influence the same for performance uplifts in upcoming revisions. Will be guiding the execution team by projecting CPUSS performance in upcoming chips and correlating them with pre-silicon runs and post silicon measurements. Responsible for driving deep dive analysis on performance issues, bottleneck providing fixes or workarounds on CPU subsystem and related SOC Modules. The ideal candidate to have a strong CPU architecture / analysis background along with overall SOC wide exposure and Embedded system concepts on modern chipsets-based ARM/X86 Essential Skills and Experience Familiar with Microprocessor and/or SoC Architecture and micro-Architecture, preferably ARM processors and ARM processor-based systems. Experience of ARM based System Designs, Knowledge of CPU and hierarchical memory system, cache configurations and coherency issues in multi-core systems . Experience with workload performance characterization, bottleneck analysis, and driving microarchitecture investigations on CPU /GPU/Systems with relevant performance matrix Hands-on with Lauterbach debug environment, Emulation platforms and experience in working with bare-metal environment with knowledge of Linux boot. Engage with architects and design teams to investigate next-generation CPU microarchitecture performance features through workload-driven investigations, especially well-known CPU benchmarks like Lmbench, Spec, Geekbench . Develop, simulate workloads for pre-silicon performance analysis and performance projections on silicon. Lead initiatives for performance technology alignment across product engineering teams Good to have Minimum 12 + years years of experience on relevant areas. Strong data analysis skills to identify performance trends from large data sets and the technical bent to investigate anomalies Understanding of Linux and Android internals from a performance point of view. Strong programming experience in at least one languageC/C++, Perl, Python Familiarity with hardware/software level performance analysis of industry standard benchmarks & open source applications. Excellent debugging skills at SoC and System level Excellent communication skills and ability to collaborate with peers and senior architects/design engineers across the globe. Familiar with pre-silicon environments such as Verification, Emulation and Virtual Bring-Up, etc. Good knowledge of high-performance microprocessor architecture and complex SoC Pre-silicon performance experience is a huge plus Post Silicon Experience and debugging on the devices using relevant Debug tools and Bus profiling tools are added advantage. Educational qualification Bachelor's degree in Electrical, Electronics or Computer Engineering and/or Computer Science, with 6+ years of experience in SOC/CPU post-silicon validation / performance analysis Strong knowledge of modern OS kernel (Android, Linux) , enable Linux/Android during bring-up

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for an experience Verification Staff/Architect Engineer, who will be responsible Verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.) which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Responsible for Quality sign off and required documentation Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis " Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM based verification Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Communication and collaboration skills to work with a large world-wide design organization " Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Qualification : Bachelor/Masters Degree in Electronics & Communication / Micro Electronics 9 -12 years of experience Experience with UVM and ARM Bus protocols. tor, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Would be working on Qualcomm Snapdragon CPUSS Architecture and performance team. Responsible for analyzing the performance aspects of Snapdragon CPU subsystem and influence the same for performance uplifts in upcoming revisions. Will be guiding the execution team by projecting CPUSS performance in upcoming chips and correlating them with pre-silicon runs and post silicon measurements. Responsible for driving deep dive analysis on performance issues, bottleneck providing fixes or workarounds on CPU subsystem and related SOC Modules. The ideal candidate to have a strong CPU architecture / analysis background along with overall SOC wide exposure and Embedded system concepts on modern chipsets-based ARM/X86 Essential Skills and Experience Familiar with Microprocessor and/or SoC Architecture and micro-Architecture, preferably ARM processors and ARM processor-based systems. Experience of ARM based System Designs, Knowledge of CPU and hierarchical memory system, cache configurations and coherency issues in multi-core systems . Experience with workload performance characterization, bottleneck analysis, and driving microarchitecture investigations on CPU /GPU/Systems with relevant performance matrix Hands-on with Lauterbach debug environment, Emulation platforms and experience in working with bare-metal environment with knowledge of Linux boot. Engage with architects and design teams to investigate next-generation CPU microarchitecture performance features through workload-driven investigations, especially well-known CPU benchmarks like Lmbench, Spec, Geekbench . Develop, simulate workloads for pre-silicon performance analysis and performance projections on silicon. Lead initiatives for performance technology alignment across product engineering teams Good to have Minimum 12 + years years of experience on relevant areas. Strong data analysis skills to identify performance trends from large data sets and the technical bent to investigate anomalies Understanding of Linux and Android internals from a performance point of view. Strong programming experience in at least one languageC/C++, Perl, Python Familiarity with hardware/software level performance analysis of industry standard benchmarks & open source applications. Excellent debugging skills at SoC and System level Excellent communication skills and ability to collaborate with peers and senior architects/design engineers across the globe. Familiar with pre-silicon environments such as Verification, Emulation and Virtual Bring-Up, etc. Good knowledge of high-performance microprocessor architecture and complex SoC Pre-silicon performance experience is a huge plus Post Silicon Experience and debugging on the devices using relevant Debug tools and Bus profiling tools are added advantage. Educational qualification Bachelor's degree in Electrical, Electronics or Computer Engineering and/or Computer Science, with 6+ years of experience in SOC/CPU post-silicon validation / performance analysis Strong knowledge of modern OS kernel (Android, Linux) , enable Linux/Android during bring-up

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of our highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle. Preferred qualifications B.E/B.Tech/M.E/M.Tech in Electronics with 5+ year experience in verification domain. Strong fundamentals in digital ASIC verification Experience in IP/SS/SoC level verification of medium to high complexity design Familiarity with system level HW and SW Debug techniques and Verification requirements A good understanding of the complete verification life cycle (test plan, testbench through coverage closure) Strong System Verilog/UVM based verification skills & Experience with Assertion & coverage-based verification methodology Experience w/ PSS or higher-level test construction languages is an added advantage Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc. Knowledge of one or more of Multimedia design blocks such as Display/Camera/Video/GFx Knowledge of one or more of peripheral blocks verification such as PCIe/USB/UFS/I3C Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Define verification architecture, develop test plans and build verification environment Work with design team to understand design intent and bring up verification plans and schedules Verify Subsystems and Full SoC using advanced verification methodologies Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard Develop test plan to verify all low power aspects across all modes of verification- RTL, PA-RTL, PA-GLS and Formal Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Assist in silicon bring-up, debug and bring-up activities

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Would be working on Qualcomm Snapdragon CPUSS Architecture and performance team. Responsible for analyzing the performance aspects of Snapdragon CPU subsystem and influence the same for performance uplifts in upcoming revisions. Will be guiding the execution team by projecting CPUSS performance in upcoming chips and correlating them with pre-silicon runs and post silicon measurements. Responsible for driving deep dive analysis on performance issues, bottleneck providing fixes or workarounds on CPU subsystem and related SOC Modules. The ideal candidate to have a strong CPU architecture / analysis background along with overall SOC wide exposure and Embedded system concepts on modern chipsets-based ARM/X86 Essential Skills and Experience Familiar with Microprocessor and/or SoC Architecture and micro-Architecture, preferably ARM processors and ARM processor-based systems. Experience of ARM based System Designs, Knowledge of CPU and hierarchical memory system, cache configurations and coherency issues in multi-core systems . Experience with workload performance characterization, bottleneck analysis, and driving microarchitecture investigations on CPU /GPU/Systems with relevant performance matrix Hands-on with Lauterbach debug environment, Emulation platforms and experience in working with bare-metal environment with knowledge of Linux boot. Engage with architects and design teams to investigate next-generation CPU microarchitecture performance features through workload-driven investigations, especially well-known CPU benchmarks like Lmbench, Spec, Geekbench . Develop, simulate workloads for pre-silicon performance analysis and performance projections on silicon. Lead initiatives for performance technology alignment across product engineering teams Good to have Minimum 5 + years years of experience on relevant areas. Strong data analysis skills to identify performance trends from large data sets and the technical bent to investigate anomalies Understanding of Linux and Android internals from a performance point of view. Strong programming experience in at least one languageC/C++, Perl, Python Familiarity with hardware/software level performance analysis of industry standard benchmarks & open source applications. Excellent debugging skills at SoC and System level Excellent communication skills and ability to collaborate with peers and senior architects/design engineers across the globe. Familiar with pre-silicon environments such as Verification, Emulation and Virtual Bring-Up, etc. Good knowledge of high-performance microprocessor architecture and complex SoC Pre-silicon performance experience is a huge plus Post Silicon Experience and debugging on the devices using relevant Debug tools and Bus profiling tools are added advantage. Educational qualification Bachelor's degree in Electrical, Electronics or Computer Engineering and/or Computer Science, with 6+ years of experience in SOC/CPU post-silicon validation / performance analysis Strong knowledge of modern OS kernel (Android, Linux) , enable Linux/Android during bring-up

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Would be working on Qualcomm Snapdragon CPUSS Architecture and performance team. Responsible for analyzing the performance aspects of Snapdragon CPU subsystem and influence the same for performance uplifts in upcoming revisions. Will be guiding the execution team by projecting CPUSS performance in upcoming chips and correlating them with pre-silicon runs and post silicon measurements. Responsible for driving deep dive analysis on performance issues, bottleneck providing fixes or workarounds on CPU subsystem and related SOC Modules. The ideal candidate to have a strong CPU architecture / analysis background along with overall SOC wide exposure and Embedded system concepts on modern chipsets-based ARM/X86 Essential Skills and Experience Familiar with Microprocessor and/or SoC Architecture and micro-Architecture, preferably ARM processors and ARM processor-based systems. Experience of ARM based System Designs, Knowledge of CPU and hierarchical memory system, cache configurations and coherency issues in multi-core systems . Experience with workload performance characterization, bottleneck analysis, and driving microarchitecture investigations on CPU /GPU/Systems with relevant performance matrix Hands-on with Lauterbach debug environment, Emulation platforms and experience in working with bare-metal environment with knowledge of Linux boot. Engage with architects and design teams to investigate next-generation CPU microarchitecture performance features through workload-driven investigations, especially well-known CPU benchmarks like Lmbench, Spec, Geekbench . Develop, simulate workloads for pre-silicon performance analysis and performance projections on silicon. Lead initiatives for performance technology alignment across product engineering teams Good to have Minimum 8 + years years of experience on relevant areas. Strong data analysis skills to identify performance trends from large data sets and the technical bent to investigate anomalies Understanding of Linux and Android internals from a performance point of view. Strong programming experience in at least one languageC/C++, Perl, Python Familiarity with hardware/software level performance analysis of industry standard benchmarks & open source applications. Excellent debugging skills at SoC and System level Excellent communication skills and ability to collaborate with peers and senior architects/design engineers across the globe. Familiar with pre-silicon environments such as Verification, Emulation and Virtual Bring-Up, etc. Good knowledge of high-performance microprocessor architecture and complex SoC Pre-silicon performance experience is a huge plus Post Silicon Experience and debugging on the devices using relevant Debug tools and Bus profiling tools are added advantage. Educational qualification Bachelor's degree in Electrical, Electronics or Computer Engineering and/or Computer Science, with 6+ years of experience in SOC/CPU post-silicon validation / performance analysis Strong knowledge of modern OS kernel (Android, Linux) , enable Linux/Android during bring-up

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Would be working on Qualcomm Snapdragon CPUSS Architecture and performance team. Responsible for analyzing the performance aspects of Snapdragon CPU subsystem and influence the same for performance uplifts in upcoming revisions. Will be guiding the execution team by projecting CPUSS performance in upcoming chips and correlating them with pre-silicon runs and post silicon measurements. Responsible for driving deep dive analysis on performance issues, bottleneck providing fixes or workarounds on CPU subsystem and related SOC Modules. The ideal candidate to have a strong CPU architecture / analysis background along with overall SOC wide exposure and Embedded system concepts on modern chipsets-based ARM/X86 Essential Skills and Experience Familiar with Microprocessor and/or SoC Architecture and micro-Architecture, preferably ARM processors and ARM processor-based systems. Experience of ARM based System Designs, Knowledge of CPU and hierarchical memory system, cache configurations and coherency issues in multi-core systems . Experience with workload performance characterization, bottleneck analysis, and driving microarchitecture investigations on CPU /GPU/Systems with relevant performance matrix Hands-on with Lauterbach debug environment, Emulation platforms and experience in working with bare-metal environment with knowledge of Linux boot. Engage with architects and design teams to investigate next-generation CPU microarchitecture performance features through workload-driven investigations, especially well-known CPU benchmarks like Lmbench, Spec, Geekbench . Develop, simulate workloads for pre-silicon performance analysis and performance projections on silicon. Lead initiatives for performance technology alignment across product engineering teams Good to have Minimum 5 + years years of experience on relevant areas. Strong data analysis skills to identify performance trends from large data sets and the technical bent to investigate anomalies Understanding of Linux and Android internals from a performance point of view. Strong programming experience in at least one languageC/C++, Perl, Python Familiarity with hardware/software level performance analysis of industry standard benchmarks & open source applications. Excellent debugging skills at SoC and System level Excellent communication skills and ability to collaborate with peers and senior architects/design engineers across the globe. Familiar with pre-silicon environments such as Verification, Emulation and Virtual Bring-Up, etc. Good knowledge of high-performance microprocessor architecture and complex SoC Pre-silicon performance experience is a huge plus Post Silicon Experience and debugging on the devices using relevant Debug tools and Bus profiling tools are added advantage. Educational qualification Bachelor's degree in Electrical, Electronics or Computer Engineering and/or Computer Science, with 6+ years of experience in SOC/CPU post-silicon validation / performance analysis Strong knowledge of modern OS kernel (Android, Linux) , enable Linux/Android during bring-up.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Would be working on Qualcomm Snapdragon CPUSS Architecture and performance team. Responsible for analyzing the performance aspects of Snapdragon CPU subsystem and influence the same for performance uplifts in upcoming revisions. Will be guiding the execution team by projecting CPUSS performance in upcoming chips and correlating them with pre-silicon runs and post silicon measurements. Responsible for driving deep dive analysis on performance issues, bottleneck providing fixes or workarounds on CPU subsystem and related SOC Modules. The ideal candidate to have a strong CPU architecture / analysis background along with overall SOC wide exposure and Embedded system concepts on modern chipsets-based ARM/X86 Essential Skills and Experience Familiar with Microprocessor and/or SoC Architecture and micro-Architecture, preferably ARM processors and ARM processor-based systems. Experience of ARM based System Designs, Knowledge of CPU and hierarchical memory system, cache configurations and coherency issues in multi-core systems . Experience with workload performance characterization, bottleneck analysis, and driving microarchitecture investigations on CPU /GPU/Systems with relevant performance matrix Hands-on with Lauterbach debug environment, Emulation platforms and experience in working with bare-metal environment with knowledge of Linux boot. Engage with architects and design teams to investigate next-generation CPU microarchitecture performance features through workload-driven investigations, especially well-known CPU benchmarks like Lmbench, Spec, Geekbench . Develop, simulate workloads for pre-silicon performance analysis and performance projections on silicon. Lead initiatives for performance technology alignment across product engineering teams Good to have Minimum 4+ years years of experience on relevant areas. Strong data analysis skills to identify performance trends from large data sets and the technical bent to investigate anomalies Understanding of Linux and Android internals from a performance point of view. Strong programming experience in at least one languageC/C++, Perl, Python Familiarity with hardware/software level performance analysis of industry standard benchmarks & open source applications. Excellent debugging skills at SoC and System level Excellent communication skills and ability to collaborate with peers and senior architects/design engineers across the globe. Familiar with pre-silicon environments such as Verification, Emulation and Virtual Bring-Up, etc. Good knowledge of high-performance microprocessor architecture and complex SoC Pre-silicon performance experience is a huge plus Post Silicon Experience and debugging on the devices using relevant Debug tools and Bus profiling tools are added advantage. Educational qualification Bachelor's degree in Electrical, Electronics or Computer Engineering and/or Computer Science, with 6+ years of experience in SOC/CPU post-silicon validation / performance analysis Strong knowledge of modern OS kernel (Android, Linux) , enable Linux/Android during bring-up

Interested Candidate drop your cv @careers9425@gmail.com or 8712631806

Specialist IS Bus Sys Analyst What you will do Let’s do this. Let’s change the world. In this vital role you will serve as a Business Systems Analyst supporting data analytics and visualization efforts across Amgen’s Global Procurement Operations . You will work with Product Owners, Data Engineers, and Business SMEs to deliver reporting and dashboards that unlock insights across Source-to-Settle processes. This role is critical to building Amgen’s analytics foundation for procurement transformation. . Roles & Responsibilities: Gather and document business reporting and analytics requirements across product teams. Design and build dashboards in tools such as Tableau, Power BI, or SAP Analytics Cloud. Translate procurement KPIs into actionable visualizations aligned with product team priorities. Collaborate with EDF and source system teams (SAP, Ariba, Apex, LevelPath) to define and access data sources. Perform data validation and user acceptance testing for new dashboards and enhancements. Enable self-service analytics capabilities for business users. Ensure compliance with Amgen’s data governance and visualization standards. What we expect of you We are all different, yet we all use our unique contributions to serve patients. Basic Qualifications: Master’s degree and 4 to 6 years of relevant experience OR Bachelor’s degree and 6 to 8 years of relevant experience OR Diploma and 10 to 12 years of professional experience. Preferred Qualifications: Must-Have Skills: Hands-on experience with Tableau, Power BI, or similar tools. Solid understanding of procurement data and Source-to-Settle processes. Ability to partner with cross-functional stakeholders to define KPIs and reporting needs. Good-to-Have Skills: Familiarity with data lake/data warehouse concepts (EDF preferred). Basic SQL or data wrangling skills to support ETL processes. Professional Certifications (Preferred): Tableau or Power BI certification; Agile certifications are a plus. Soft Skills: Exceptional communication and stakeholder management skills. Ability to collaborate across global teams and influence outcomes. Strong organizational skills to manage multiple priorities. Team-oriented and focused on delivering high-value solutions. Self-starter with a proactive approach to resolving challenges and driving innovation. What you can expect of us As we work to develop treatments that take care of others, we also work to care for your professional and personal growth and well-being. From our competitive benefits to our collaborative culture, we’ll support your journey every step of the way. In addition to the base salary, Amgen offers competitive and comprehensive Total Rewards Plans that are aligned with local industry standards. Apply now and make a lasting impact with the Amgen team. careers.amgen.com As an organization dedicated to improving the quality of life for people around the world, Amgen fosters an inclusive environment of diverse, ethical, committed and highly accomplished people who respect each other and live the Amgen values to continue advancing science to serve patients. Together, we compete in the fight against serious disease. Amgen is an Equal Opportunity employer and will consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability status, or any other basis protected by applicable law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

Qualification: BE/ME/M-Tech Mechanical Experience Range: 3 to 6 Years Work Location - Bangalore Notice period - candidate should join us with in 2 weeks. Share Updated Resume to - yuvashree.thiyagarajan@asmltd.com Roles & Responsibilities: Design of Chassis aggregates and chassis attachment, etc. Design/solution identification as per requirement and align within cross functional department, also interaction with development partners Must Have: 1.Chassis Attachment Systems: Knowledge of systems like Lateral Protection device, Fuel Tank Mounting, Battery mounting, spare wheel mounting, Rear Mud guard Mounting, Footsteps. Knowledge of Chassis Attachment parameters and design validation. Proficiency in Chassis Design 2. Technical Skills: Proficiency in Creo (part design SMD, GSD, assembly, drawings). Understanding of Manufacturing process: sheet metal, casting, machining. Good knowledge of GD&T and tolerance stack-up. 3. Interpersonal Skills and Analytical Skills: • Excellent communication, presentation, and teamwork skills. Strong analytical and technical communication skills. 4. Standards and Processes: Knowledge of homologation standards and product development cycle. Ability to document designs in PLM and generate bill of materials. 5. Project Management: Align technical requirements with project team. Prepare for technical reviews. Organize and prioritize workload. Propose project timelines and efforts. Regards Yuvashree Thiyagarajan yuvashree.thiyagarajan@asmltd.com 6369701096

We are seeking a highly experienced and innovative Solution Architect with expertise in Java and AWS technologies to lead the design and implementation of scalable, high-performance solutions. This role offers an exciting opportunity to work on cutting-edge projects in cloud-native and microservices architectures while collaborating directly with clients and cross-functional teams. Responsibilities Translate business requirements into scalable, secure, and cost-effective solutions aligned with enterprise standards Define architecture vision across application, integration, and infrastructure layers, ensuring alignment with business goals Apply industry best practices and patterns, including microservices, serverless, and event-driven architectures Create and maintain detailed architecture documentation such as solution design diagrams, narratives, and work breakdown structures Facilitate technical brainstorming sessions, architecture workshops, and whiteboarding exercises with teams and stakeholders Conduct technical reviews, design validations, and walkthroughs of solution proposals with customers Lead decision-making processes for architecture spanning data, security, scalability, and integration domains Drive modernization initiatives by utilizing modern technology stacks and approaches for greenfield projects Oversee alignment with non-functional requirements (NFRs) such as performance, security, scalability, and high availability Collaborate in the adoption of architectural quality frameworks like Utility Trees and Quality Attribute Workshops Manage architectural complexities in cloud-native and serverless applications to ensure robust design principles are adhered to Requirements 13–19 years of professional experience with strong understanding of enterprise-scale solutions Proven expertise in Java 11/17+, Spring Boot, Spring Cloud, RESTful APIs, and microservices architecture Strong implementation knowledge of AWS services including Lambda, EC2, S3, RDS, API Gateway, Step Functions, SNS/SQS Completion of at least 3 solution architecture projects over the past 5 years Background in designing and building cloud-native applications and serverless solutions Showcase of driving architectural decisions across complex domains like data, security, and integration Experience in customer-facing technical discussions, architecture workshops, and reviews Familiarity with non-functional requirements such as security, scalability, high availability, and performance optimization Understanding of architectural quality frameworks including Utility Trees and Quality Attribute Workshops

SUMMARY Job Opportunity for Lorry Driver Job Responsibilities Safely transport goods and materials to various locations, both locally and nationally. Conduct routine inspections and maintenance checks on the vehicle before and after trips. Ensure precise loading and unloading of goods, including securing cargo to prevent damage. Efficiently plan routes using maps or GPS to meet delivery deadlines. Maintain delivery records, logbooks, and tachographs in compliance with legal standards. Adhere to company policies and all road safety and traffic regulations. Promptly report mechanical issues or incidents to fleet management. Maintain communication with dispatchers and clients to provide delivery updates. Deliver courteous and professional service to clients during delivery. Assist with paperwork related to shipping, receiving, and invoicing. Requirements Requirements: Valid HGV/LGV driving license. Certificate of Professional Competence (CPC) qualification. 3+ years of working experience as a lorry or truck driver. Clean driving record with no major traffic violations. Good knowledge of road safety regulations and HGV driving hours. Ability to handle physical tasks, including lifting and securing cargo. Strong time management and organizational skills. Basic mechanical knowledge for performing minor repairs and checks. Reliable, punctual, and capable of working independently. Good communication skills and customer-focused attitude.

Team O3Hire is managed by a professionals in the domain of Human Resources holding valuable experience. The founding team is dynamic and adaptable to business needs and aspires to eliminate unemployment. We've bought you the excellent opportunity to plug yourself with one of the leading brands into Automobile Industry . Below are the basic points for your understanding: Positions : Service Engineer Locations : Gurgaon Qualification needed : B.Tech/ B.E/ Diploma Basic Key Points: 1. Responsible for execution of Live Trials targeting accurate (customer validated) data, superior vehicle performance, professional customer experience and reporting 2. Establishing CVP for target customers, products and applications. 3. Resolving CVP complaints - Ensure any vehicle performance/ value delivery dispute with customer is resolved. And secure solution on technical issues if any from Aftermarket 3. Support the Sales team a. Interviewing customers, fleet managers and drivers to collate data for OPECO and CPOL studies b. Train stake holders like fleet managers, drivers to ensure best utilization of the product features c. Work with the customer and stake holders to establish the CVP committed in the business proposal d. Train the customer and users in telematics. Handholding to realize full potential of telematics e. Monthly monitoring of performance with all customers to ensure sustainability of signed off profitability. Intervene wherever required f. Monthly reporting of customer wise profitability g. In-depth study and understanding of various usage segments 4. Develop the dealer PCs/ competency in dealer sales organization to: a. Conduct professional demos b. Create business proposals c. Track and monitor vehicle performance and CVP d. Help the customer derive benefit from various truck features e. Help the customer drive Eicher Telematics f. Report customer wise profitability ... Regards, Pooja Team O3Hire +91-9875971749 pooja@o3hire.com

Role & responsibilities Experience of 2 to 6 years in Wiring Harness design for the automotive industry using UG NX. Should be able to execute: Experience with UG NX in Wiring Harness with 2 to 6 years of experience. Create 3D Designs for low Voltage/High Voltage Wiring Harnesses considering EMC requirements. Must have Wiring harness domain knowledge and knows component selection criteria Create 2D Drawings for Low Voltage/High Voltage Wiring Harness Detecting/Determining of suitable wiring materials, shielding, protections based on surrounding parts/geometry Develop effective routing paths of 3D Model with the help of retainers, channels, grommets, etc.. Design brackets, trays, enclosures, grommets and other components to support wiring harness design and electrical modules packaging. Basic Knowledge of 2D drawing & 3D DMU Automotive Domain experience Good communication skills and ability to work in & contribute as a good team player.

Long Description Job Summary Incumbent should be from an Engineering industry into Steel Fabrication & Industrial Racking production with minimum 2-5 years of experience and would be responsible for Production output, Safety, Discipline, Attendance, Absenteeism and Total Shift activity Job Responsibilities Handling of dedicated production activities/sub contract activities. Providing daily production. Plate cutting knowledge, bus body fabrication, and industrial racking fabrication will be preferred. Responsible for handling the complete shift operations and managing the workmen. Ensure the total loading operations carried out as per plan in a shift. Meeting the target of shipment as per the priorities set from time to time by monitoring the activities of checkers and operators. Verifying and confirming the shipper details while vehicles are being loaded in a shift. Monitoring the attendance of workmen in the shift and work allotment as per plan Strictly follow the priority (Jobs or Part marks) while loading Verifying the jobs before loading Ensuring the phase wise closing of the jobs as planned Should leave the work spot only after reliever takes the charge Educating the operators and chakkars towards priority items Candidate Requirements Age Range: 24-30 years 2-5 years in managing the workforce in manufacturing / engineering industry Supervisory skills Understanding the priority requirements Should be able to meet the targets set from time to time Manage the workmen and educate them with the requirements of job Go-getter, good at communication, influencing and convincing skills, good at People Management Education Diploma Bachelor s Degree