RTL Engineers - PCIe

Role Overview

This is a design-focused role centered on PCIe microarchitecture, protocol logic, and high-performance datapath development. The focus is on architecting and implementing PCIe functionality, not subsystem or IP integration.

Responsibilities

• Provide technical leadership for PCIe microarchitecture and RTL execution, ensuring robust design and adherence to performance, power, and area goals.

• Develop high-performance PCIe buffering, schedulers, and protocol engines.

• Own RTL development, including coding, documentation, code reviews, lint/CDC readiness, and block-level debug.

• Collaborate with Verification to define test plans, PCIe VIP usage, coverage goals, and debug complex protocol behaviors.

• Collaborate with Physical Design for timing closure in synthesis and place-and-route.

• Support post-silicon PCIe bring-up and validation focused on protocol correctness, link behavior, and subsystem performance.

• Collaborate with system and chip architects to ensure PCIe subsystem behavior aligns with chip-level bandwidth, latency, and power objectives.

• Partner with Architecture, DV, and Physical Design teams to achieve power, performance, and timing closure targets.

Qualifications

• MSEE with

  15+ years

  of ASIC/SoC RTL design experience.

• Proven success designing PCIe controller or PCIe protocol logic (Gen4/Gen5/Gen6).

• Deep knowledge of PCIe LTSSM, TLP/FLIT pipelines, flow control, ordering rules, error mechanisms, and performance tuning.

• Strong RTL design skills with experience in multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning.

• Familiarity with SerDes behavior (equalization, training sequences) as required for correct PCIe protocol implementation.

• Familiarity with full ASIC design flow (DFT, synthesis, timing, and physical implementation considerations).

• Excellent analytical, problem-solving, and communication skills, with the ability to drive cross-functional technical execution.