Physical Design Engineer

Job Title: Physical Design Engineer
Location: Hyderabad, TG / Bangalore, KAJob Type: Permanent/Fulltime (Hybrid)Client: Capgemini (Payroll: MLE Systems)Experience: 8 Years (Senior Welcome)Budget: 40 LPA (Depends on Experience)Interview: Microsoft Teams (L1+L2)Role 1: Physical Design Engineer - LeadKey Responsibilities:Own and drive floorplanning for complex SoC or IP blocks from RTL to GDSII.Collaborate with RTL, DFT, and architecture teams to understand design requirements and translate them into optimal floorplans.Perform macro placement, power grid planning, pin placement, and block-level partitioning.Analyse and optimize for congestion, timing, area, and power.FEV debug and closure.CLP sign-off.Low power optimization and UPF development.Work closely with place & route, clock tree synthesis, and timing closure teams to ensure floorplan quality.STA sign-off.IR drop analysis and EM verification.Physical verification sign-off.Required Skills:Strong hands-on experience with EDA tools like Cadence Innovus, Synopsys ICC2, or Mentor Olympus.Deep understanding of physical design flow, especially floorplanning, placement, routing, and STA.Experience in hierarchical design, multi-voltage domains, and power planning.Good knowledge of timing analysis, signal integrity, and DFT-aware floorplanning.Proficiency in scripting (Tcl, Perl, Python) for automation and debugging.Familiarity with Physical verification tools such as Calibre.Role 2: Synthesis, Constraints, STA - LeadKey Responsibilities:Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.Experience with writing timing constraints for synthesis, STA, timing closure, and pipelining at different levels for performance optimization and timing closure.Experience in all aspects of timing closure for multi-clock domain designs.Should be familiar with MCMM synthesis and optimization.Should have good understanding of low-power design implementation using UPF.Experience with scripting language such as Perl/ Python, TCL.Experience with different power optimization flows or technique such as clock gating.Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation.Should be able to handle ECOs and formal verification and maintain high quality matrix. Should have deep Knowledge in Formal Verification(LEC) and Debugging Non-equivalence checksRequired Skills:Strong hands-on experience with EDA tools like Cadence Innovus, Synopsys ICC2, or Mentor Olympus.Deep understanding of physical design flow, Primetime.Experience in hierarchical design, multi-voltage domains, and timing closure.Proficiency in scripting (Tcl, Perl, Python) for automation and debugging. 📧: sayan.dey@deybiz.com