Physical Design Engineer

Job Title: Physical Design Engineer (ASIC / SoC / Mixed-Signal)

Experience: 5 – 15 years

Location: Bangalore

Job Type: Full-time

About the Role:

We are looking for an experienced Physical Design Engineer to join our backend/layout implementation team. The ideal candidate will work on translating RTL/netlist designs into production-ready physical layouts while optimizing for PPA, timing closure, signal integrity, and manufacturability. This role requires solid hands-on experience in ASIC/SoC Physical Design flows and tape-out.

Key Responsibilities:

Drive the complete Physical Design flow from netlist to GDSII: floorplanning, placement, routing, CTS, optimization.

Perform Static Timing Analysis (STA), timing closure, IR/EM analysis, and power/signal integrity verification.

Own DRC/LVS sign-off and resolve all physical design issues across stages.

Collaborate closely with design, verification, and manufacturing teams to ensure smooth tape-out delivery.

Develop and enhance automation scripts and design flows using TCL, Python, Perl, Shell.

Optimize blocks and full-chip design for PPA (Power, Performance, Area) and manufacturability.

Provide technical guidance and mentor junior engineers; participate in reviews and design discussions.

Required Qualifications:

Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering or related field.

5–15 years of hands-on experience in ASIC/SoC Physical Design (digital or mixed-signal).

Prior tape-out experience is highly preferred.

Required Technical Skills:

Expertise in EDA tools such as Synopsys ICC2, Cadence Innovus, Mentor, PrimeTime, and sign-off tools.

Strong understanding of VLSI design flow, STA, power/area optimization, clock-tree synthesis (CTS), routing, SI/PI, and DRC/LVS rules.

Strong scripting knowledge: TCL, Python, Perl, Shell for flow automation.

Excellent analytical and problem-solving skills with the ability to work in cross-functional teams.

Preferred Skills: (Good to Have)

Experience with low-power design techniques (UPF/CPF).

Knowledge of IR/EM and advanced power analysis methodologies.

Leadership, mentoring, or project-level ownership experience.