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ACL Digital
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Physical Design Engineer

Physical Design Engineer

ACL Digital

4 years

0 Lacs

bengaluru karnataka india

Posted:15 hours ago| Platform:

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Skills Required

design targeting power optimization synthesis routing timing drc lvs drive verification dft analysis reports support electrical cadence synopsys compiler siemens scripting tcl perl python flow grid

Work Mode

On-site

Job Type

Full Time

Job Description

Job Title:

Experience:

Location:

Employment Type:

Industry:

Job Summary:

Physical Design Engineer

Key Responsibilities:

Own block-level or full-chip implementation from RTL to GDSII.
Perform:
Floorplanning and placement
Clock tree synthesis (CTS)
Routing and optimization
Run and close timing (STA), IR drop, EM, DRC, LVS, and antenna checks.
Drive physical verification and signoff across various corners and scenarios.
Collaborate with RTL, DFT, STA, and power teams for successful integration.
Implement and debug low-power design techniques (UPF/CPF-based flows).
Apply congestion analysis, ECOs, and timing fixes across critical paths.
Optimize for performance, power, and area using EDA tools and foundry guidelines.
Prepare design reports and support tapeout activities.

Required Skills and Experience:

B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Design.
4+years of experience in ASIC physical design.
Strong hands-on experience with tools like:
Place & Route:
Cadence Innovus, Synopsys IC Compiler II (ICC2), Siemens Nitro
STA:
Synopsys PrimeTime
Signoff:
Calibre (DRC/LVS), RedHawk (IR/EM), Tempus
Good understanding of physical design concepts: floorplan, placement, CTS, routing, ECO, and signoff.
Familiarity with scripting languages: Tcl, Perl, Python for flow automation.
Solid grasp of timing analysis, power grid design, and physical verification flows.

Interested can share Cv to Sharmila.b@acldigital.com

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