Functional Verification Engineer UVM

Screen2Hire Consulting LLP

3 - 7 years

0 Lacs

noida uttar pradesh

Posted:1 day ago| Platform: Shine logo

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Skills Required

systemverilog uvm ip microarchitecture assertions vcs questa rtl dft firmware simvision bug tracking jira bugzilla functional verification engineer rtl designs testbenches functional coverage soclevel designs directed tests constrainedrandom tests functional coverage sva checkers simulators xcelium waveforms dve

Work Mode

On-site

Job Type

Full Time

Job Description

As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM. Your role involves developing testbenches, building reusable components, and ensuring complete functional coverage of IPs or SoC-level designs. Key Responsibilities: - Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification - Create test plans from microarchitecture/design specifications - Write and debug directed and constrained-random tests - Implement functional coverage, assertions (SVA), and checkers - Run regressions using simulators like VCS, Xcelium, or Questa - Interface with RTL, DFT, and Firmware teams to track and resolve bugs - Analyze waveforms (using DVE/SimVision), track bugs, and maintain bug databases (JIRA, Bugzilla) Qualifications Required: - B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design Please note that the job type is Full-time and Permanent, with a Day shift schedule and the work location is in person.,

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Functional Verification Engineer UVM