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3.0 - 7.0 years
0 Lacs
noida, uttar pradesh
On-site
As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM. Your role involves developing testbenches, building reusable components, and ensuring complete functional coverage of IPs or SoC-level designs. Key Responsibilities: - Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification - Create test plans from microarchitecture/design specifications - Write and debug directed and constrained-random tests - Implement functional coverage, assertions (SVA), and checkers - Run regressions using simulators like VCS, Xcelium, or Questa - Interface with RTL, DFT, and Firmware teams to track and resolve bugs - Analyze wavefo...
Posted 3 days ago
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