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ASIC Design Verification Engineer - SystemVerilog, UVM test bench Cisco

6.0 - 11.0 years

8 - 13 Lacs

Bengaluru

Work from Office

Your Impact Develop test plans, cover points, and qualification tests Perform end-to-end verification of design blocks and top-level Build and maintain block, cluster, and top-level DV environment infrastructure Construct testbenches components like scoreboard, agents, sequencers, and monitors Write tests, debug regressions, and drive to module verification closure Collaborate with designers and verification engineers for cross-block verification Upgrade configuration/reset sequences (APIs) Develop environment and tests for emulation Ensure complete verification coverage through code, functional coverage, and gate level simulations Support post-silicon bring-up and optimize integration and performance Minimum Qualifications Bachelors Degree in EE, CE, or other related fields with 6+ years or Masters Degree with 4+ years of ASIC design or verification experience Experience in developing verification environment for complex blocks from design specifications document Proficient in verifying complex blocks and/or clusters for ASIC using UVM/System Verilog. Scripting experience with Perl, Python, TCL, shell scripts. Preferred Qualifications Experience in Data center/ Hyper scaler /AI Networking technologies Proven experience meeting and delivering project milestones and deadlines. Ability to communicate technical concepts to audiences spanning executives to junior engineers to customers. Demonstrated ability in troubleshooting and debugging. Experience with Emulation and Formal Verification tools is a plus.

Posted 2 weeks ago

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