4 Dve Jobs

Lead the verification planning and execution for complex SoC designs. Define and implement testbenches using SystemVerilog/UVM methodologies. Work closely with architecture, design, and firmware teams to understand the design and develop test strategies. Drive block-level and full-chip verification , including IP integration . Perform coverage analysis , debug , and triage failures . Develop and maintain automation scripts to improve verification workflows. Mentor and guide junior verification engineers and drive best practices across the team. Ensure delivery on schedule with high quality and coverage metrics.

Job Specs : We are seeking a highly skilled and motivated ASIC Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore, Pune. Malaysia, Singapore Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering Visa / work permit sponsored for immediate hires Expertise in ASIC SOC verification Expertise in PCie Expertise in UVM, System Verilog and constrained random testing. Expertise in testbench architecture and SOC-level verification strategies. Expertise with protocols such as AXI, AHB, APB, USB, or DDR. Expertise with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa. Familiar with waveform debugging tools such as Verdi or DVE. Working knowledge of low-power verification (UPF) and DFT / scan concepts. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Job Specs : Develop and maintain full-chip verification environments using SystemVerilog UVM methodology. Define and execute test plans for SoC-level functionality, power intent (UPF), coherency, performance and interconnect protocols (e.g., AXI/ACE). Work closely with the RTL, DV, and integration teams to ensure complete coverage of functional and architectural features. Implement and manage stimulus generators, scoreboards, monitors, and checkers at full-chip level. Perform debugging, waveform analysis, and triage of failures in RTL simulations. Ensure code coverage and functional coverage goals are met and signoff criteria are satisfied. Collaborate with firmware/software and post-silicon teams to align verification efforts and resolve issues. Participate in formal verification, assertion-based verification, and low-power simulations. Support regression testing, issue tracking, and coverage closure. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Specs : We are seeking a highly skilled and motivated ASIC SOC & GLS Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Remote, Work From Anywhere Work Expertise: 7 Years 10 Years Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. Expertise in ASIC SOC verification. Expertise in UVM, System Verilog and constrained random testing. Expertise in Gate Level Simulation tools (GLS) or verification related to display port or memory controller Expertise in testbench architecture and SOC-level verification strategies. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Preferred immediate hires only Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Your Impact Develop test plans, cover points, and qualification tests Perform end-to-end verification of design blocks and top-level Build and maintain block, cluster, and top-level DV environment infrastructure Construct testbenches components like scoreboard, agents, sequencers, and monitors Write tests, debug regressions, and drive to module verification closure Collaborate with designers and verification engineers for cross-block verification Upgrade configuration/reset sequences (APIs) Develop environment and tests for emulation Ensure complete verification coverage through code, functional coverage, and gate level simulations Support post-silicon bring-up and optimize integration and performance Minimum Qualifications Bachelors Degree in EE, CE, or other related fields with 6+ years or Masters Degree with 4+ years of ASIC design or verification experience Experience in developing verification environment for complex blocks from design specifications document Proficient in verifying complex blocks and/or clusters for ASIC using UVM/System Verilog. Scripting experience with Perl, Python, TCL, shell scripts. Preferred Qualifications Experience in Data center/ Hyper scaler /AI Networking technologies Proven experience meeting and delivering project milestones and deadlines. Ability to communicate technical concepts to audiences spanning executives to junior engineers to customers. Demonstrated ability in troubleshooting and debugging. Experience with Emulation and Formal Verification tools is a plus.