5 Rtl Designs Jobs

As a Design Verification Engineer with over 5 years of experience, particularly in HBM & DDR DRAM IP and Subsystem verification, you will be an integral part of our innovative team. Your role will involve developing and executing verification plans, creating testbenches, and collaborating with design engineers to ensure high-quality and robust designs. Your responsibilities will include developing comprehensive verification plans for HBM4/4e IP and Subsystem, creating and maintaining testbenches using System Verilog and UVM methodology, performing functional verification of RTL designs, and resolving design and verification issues. You will also generate verification metrics, participate in design reviews, and stay updated with the latest verification technologies. To excel in this role, you should hold a Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field, have 5+ years of experience in design verification, and possess knowledge of verification languages and methodologies. Proficiency in System Verilog, UVM, and scripting languages for automation is essential. Strong problem-solving skills, attention to detail, and effective communication and teamwork abilities are crucial for success in this position. Additionally, you will be expected to mentor junior verification engineers, provide technical guidance, and contribute to the continuous improvement of verification efficiency and effectiveness. Your proven track record of successfully verifying complex IP blocks and subsystems will be highly valued in this role.,

You should have experience in developing RTL Designs using VHDL or Verilog languages within environments with constrained timing and memory resources. Your responsibilities will include designing and implementing reusable code, conducting design and code reviews, and testing and validating product implementations. You should also have a good understanding of high-level and low-level software requirements and be capable of developing software verification test cases and procedures. Additionally, you will be required to analyze and enhance the efficiency, stability, and scalability of system resources. It is important to have knowledge of embedded systems serial protocols such as UART, USB, SPI, I2C, and CAN. You will need to integrate and validate new product designs, support software QA, optimize I/O performance, and provide post-production support. Interface with hardware design and development is also a part of the role, along with improving system efficiency and stability after development. Requirements and skills for this position include a Bachelor's degree in Electrical/Electronics/Computer Engineering, Computer Science, or a related field, along with 2-5 years of industry experience. Hands-on experience in RTL design in Verilog, VHDL, and FPGA is necessary. Familiarity with Intel, Xilinx, Altera, Microsemi FPGA parts and tools, RTL debug experience, and knowledge of industry standard protocols like I2C, SPI, UART, PCIe, MIPI, AXI, and Ethernet are also required. You should have the ability to read schematics and data sheets for components, strong interpersonal and writing skills, and the capability to work both in a team and independently. Being self-motivated and passionate about work and embedded systems is essential. Experience in RTL design in Verilog, VHDL, FPGA, and in domains like Railway/Aerospace/Defence or equivalent, along with knowledge of Radio Communication Sub-systems, FPGA/RFSOC is an added advantage. If you meet the specified criteria and are interested in this position, you can apply by sending your details to kavdev@arecaembedded.in.,

NK Securities Research is a leading financial firm that leverages cutting-edge technology and sophisticated algorithms to trade the financial markets. Founded in 2011, we have gained invaluable experience in the field of High-Frequency Trading across different asset classes. As an FPGA Developer at NK Securities Research, your primary responsibility will be to design, implement, and rigorously test RTL (Register-Transfer Level) designs to power our high-frequency trading strategies. Your contributions will be instrumental in reducing system latency and enhancing performance, directly influencing trading outcomes. You will be tasked with developing high-performance RTL designs using VHDL or Verilog for FPGA-based systems, optimizing hardware implementations for ultra-low latency and high throughput, and ensuring thorough functional and timing testing of RTL designs to meet specifications. Additionally, you will be responsible for debugging and resolving issues using FPGA debugging tools such as SignalTap, ChipScope, or ModelSim. Collaboration with hardware and software teams to seamlessly integrate FPGA solutions with the Software Trading Stack will be a key aspect of your role. Maintaining clear and comprehensive documentation of designs, test cases, results, and benchmarks is essential to ensure effective communication and knowledge sharing within the team. Preferred qualifications for this role include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field from top IITs. Proficiency in VHDL or Verilog/SystemVerilog, hands-on experience with industry-standard tools like Xilinx Vivado, expertise in writing testbenches and conducting simulation-based verification, familiarity with static timing analysis, and proficiency in debugging tools such as SignalTap, ChipScope, or ModelSim are desired. Exposure to high-speed interfaces like PCIe, Ethernet, or DDR, as well as a basic understanding of low-latency design principles and architecture, are considered advantageous. Candidates with a proven track record in delivering high-quality RTL designs, strong analytical and problem-solving skills, and the ability to work independently while collaborating effectively in a team environment are encouraged to apply. In return, NK Securities Research offers a competitive salary package, the opportunity to work in a dynamic and collaborative environment, career growth and development opportunities, catered breakfast and lunch, an annual international trip, and monthly team dinners.,

The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics IP. You will: Oversee all verification activities for a GPU component or subsystem, from initial planning to final sign-off. Develop verification plans and build, maintain UVM testbench components. Monitor, track, and report verification metrics to ensure closure. Provide verification-focused feedback during design specification discussions. Implement UVM testbenches, including writing tests, sequences, functional coverage, assertions, and verification plans. Take ownership of task definition, effort estimation, and progress tracking. Contribute to the enhancement and evolution of GPU verification methodologies. Lead, mentor, and support team members in verification activities. Engage in design and verification reviews, suggesting improvements where necessary. About you Committed to making your customers, stakeholders and colleagues successful, youre an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. Youre curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You'll have: Demonstrated experience in developing verification environments for complex RTL designs. Strong understanding of constrained-random verification methodologies and the challenges of achieving verification closure. Ability to define verification requirements, determine implementation approaches, and design testbenches. Expertise in root-cause analysis of complex issues, with the ability to resolve them efficiently. Deep knowledge of SystemVerilog and UVM. Capability to develop and enhance verification flows. Familiarity with ASIC design methodologies, flows, and tools. Proficiency in planning, estimating, and tracking personal tasks. Experience managing multiple projects simultaneously. Strong communication skills for effectively conveying technical issues, both verbally and in writing. You might also have: Experience leading teams. Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++. Understanding of functional safety standards such as ISO26262.

4+ years of experience in RTL design and verification. Proven experience with digital logic design using Verilog, VHDL, or System Verilog. Experience with simulation tools such as VCS, QuestaSim, or similar. Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus). Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog. Implement complex digital functions and algorithms in RTL. Create and execute detailed test plans to verify RTL designs. Proficiency in writing and debugging RTL code. Experience with synthesis, static timing analysis, and linting tools.