7 Rtl Designs Jobs

The position is with one of our IDM client. As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM. You will develop testbenches, build reusable components, and ensure complete functional coverage of IPs or SoC-level designs. Key Responsibilities: - Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification - Create test plans from microarchitecture/design specifications - Write and debug directed and constrained-random tests - Implement functional coverage, assertions (SVA), and checkers - Run regressions using simulators like VCS, Xcelium, or Questa - Interface with RTL, DFT, and Firmware teams to track and res...

As a Design Verification Engineer with over 5 years of experience, particularly in HBM & DDR DRAM IP and Subsystem verification, you will be an integral part of our innovative team. Your role will involve developing and executing verification plans, creating testbenches, and collaborating with design engineers to ensure high-quality and robust designs. Your responsibilities will include developing comprehensive verification plans for HBM4/4e IP and Subsystem, creating and maintaining testbenches using System Verilog and UVM methodology, performing functional verification of RTL designs, and resolving design and verification issues. You will also generate verification metrics, participate in ...

You should have experience in developing RTL Designs using VHDL or Verilog languages within environments with constrained timing and memory resources. Your responsibilities will include designing and implementing reusable code, conducting design and code reviews, and testing and validating product implementations. You should also have a good understanding of high-level and low-level software requirements and be capable of developing software verification test cases and procedures. Additionally, you will be required to analyze and enhance the efficiency, stability, and scalability of system resources. It is important to have knowledge of embedded systems serial protocols such as UART, USB, SP...

NK Securities Research is a leading financial firm that leverages cutting-edge technology and sophisticated algorithms to trade the financial markets. Founded in 2011, we have gained invaluable experience in the field of High-Frequency Trading across different asset classes. As an FPGA Developer at NK Securities Research, your primary responsibility will be to design, implement, and rigorously test RTL (Register-Transfer Level) designs to power our high-frequency trading strategies. Your contributions will be instrumental in reducing system latency and enhancing performance, directly influencing trading outcomes. You will be tasked with developing high-performance RTL designs using VHDL or V...

The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics IP. You will: Oversee all verification activities for a GPU component or subsystem, from initial planning to final sign-off. Develop verification plans and build, maintain UVM testbench components. Monitor, track, and report verification metrics to ensure closure. Provide verification-focused feedback during design specification discussions. Implement UVM testbenches, including writing tests, sequences, functional c...

4+ years of experience in RTL design and verification. Proven experience with digital logic design using Verilog, VHDL, or System Verilog. Experience with simulation tools such as VCS, QuestaSim, or similar. Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus). Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog. Implement complex digital functions and algorithms in RTL. Create and execute detailed test plans to verify RTL designs. Proficiency in writing and debugging RTL code. Experience with synthesis, static timing analysis, and linting tools.

4+ years of experience in RTL design and verification. Proven experience with digital logic design using Verilog, VHDL, or System Verilog. Experience with simulation tools such as VCS, QuestaSim, or similar. Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus). Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog. Implement complex digital functions and algorithms in RTL. Create and execute detailed test plans to verify RTL designs. Proficiency in writing and debugging RTL code. Experience with synthesis, static timing analysis, and linting tools.