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2.0 - 6.0 years
0 Lacs
noida, uttar pradesh
On-site
The position is with one of our IDM client. As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM. You will develop testbenches, build reusable components, and ensure complete functional coverage of IPs or SoC-level designs. Key Responsibilities: - Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification - Create test plans from microarchitecture/design specifications - Write and debug directed and constrained-random tests - Implement functional coverage, assertions (SVA), and checkers - Run regressions using simulators like VCS, Xcelium, or Questa - Interface with RTL, DFT, and Firmware teams to track and res...
Posted 2 months ago
 
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