Home
Jobs
Companies
Resume

Functional Verification Engineer – UVM

0 years

5 - 15 Lacs

Noida

Posted:2 days ago| Platform:

Apply

Skills Required

verification systemverilog ip test design interface dft resolve analyze jira electrical

Work Mode

On-site

Job Type

Full Time

Job Description

The position is with one of our IDM client. Job Summary: As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM . You’ll develop testbenches, build reusable components, and ensure complete functional coverage of IPs or SoC-level designs. Key Responsibilities: Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification Create test plans from microarchitecture/design specifications Write and debug directed and constrained-random tests Implement functional coverage , assertions (SVA), and checkers Run regressions using simulators like VCS, Xcelium, or Questa Interface with RTL, DFT, and Firmware teams to track and resolve bugs. Analyze waveforms (using DVE/SimVision), track bugs, and maintain bug databases (JIRA, Bugzilla) Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design Job Types: Full-time, Permanent Pay: ₹520,585.58 - ₹1,589,173.72 per year Schedule: Day shift Work Location: In person

More Jobs at Screen2Hire Consulting LLP

Functional Verification Engineer – UVM

Noida

Experience: Not specified

|

INR 5 - 15 Lacs

Mock Interview

Practice Video Interview with JobPe AI

Start Verification Interview Now

My Connections Screen2Hire Consulting LLP

Download Chrome Extension (See your connection in the Screen2Hire Consulting LLP )

chrome image
Download Now
Screen2Hire Consulting LLP

RecommendedJobs for You

Functional Verification Engineer – UVM

Screen2Hire Consulting LLP

Noida

Functional Verification Engineer – UVM

Screen2Hire Consulting LLP

Noida