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4.0 - 6.0 years
0 Lacs
ahmedabad, gujarat, india
On-site
Job Summary We are seeking a highly skilled Emulation Engineer with strong experience in pre-silicon validation and hardware emulation platforms such as Palladium, Protium, Veloce, Zebu, or EP. The ideal candidate will be responsible for emulation bring-up, design build flow setup, debug, and performance tuning of complex SoCs or IP subsystems. This role involves close collaboration with design, verification, and software teams to accelerate the validation process using emulation platforms. Roles And Responsibilities Work on emulation bring-up, build flows, and model compilation for large SoC or IP-level designs. Develop and maintain emulation test environments using supported emulation plat...
Posted 1 day ago
8.0 - 12.0 years
10 - 14 Lacs
bengaluru
Work from Office
BE/ME in ECE, Electronics, or equivalent 8-12 years of experience in RTL design verification for Block/IP/Sub-system/SOC Knowledge in synthesis and timing analysis Experience with FPGA verification - Advantage Experience & Knowledge with verilog and System Verilog for Verification , SVA, UVM - Strong Advantage Deep knowledge of the following tools is an advantage: cadence NCSim, simvision, vmanager, any simulator, and waveform debug EDA tools from mentor, Synopsys Knowledge simulation environment System Verilog - UVM based advantage Developing testbench for constraint random environment, Metric driven verification Root-cause design issue and able explain in text form clearly with design know...
Posted 1 week ago
3.0 - 7.0 years
0 Lacs
noida, uttar pradesh
On-site
As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM. Your role involves developing testbenches, building reusable components, and ensuring complete functional coverage of IPs or SoC-level designs. Key Responsibilities: - Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification - Create test plans from microarchitecture/design specifications - Write and debug directed and constrained-random tests - Implement functional coverage, assertions (SVA), and checkers - Run regressions using simulators like VCS, Xcelium, or Questa - Interface with RTL, DFT, and Firmware teams to track and resolve bugs - Analyze wavefo...
Posted 2 weeks ago
3.0 - 5.0 years
0 Lacs
hyderabad, telangana, india
On-site
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop?stdcells?architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/...
Posted 1 month ago
3.0 - 5.0 years
0 Lacs
hyderabad, telangana, india
On-site
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Characterization Engineer, you will work with a highly innovative and motivated design team using state of the art memory technologies to develop the most advanced DRAM and Emerging memory products. You will be challenged by the complexity and difficulty of verifying high density memory chips with huge scale of circuit capability, ultra-high-speed designs, complex functionality which inclu...
Posted 1 month ago
4.0 - 10.0 years
0 Lacs
india
On-site
Key Responsibilities: Develop and execute verification test plans based on design specifications. Create constrained-random and directed testbenches using SystemVerilog/UVM. Develop functional coverage models and drive coverage closure. Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues. Perform block-level and/or SoC-level verification. Integrate and verify 3rd-party IPs and custom IPs in subsystem and full-chip environments. Collaborate with RTL, DFT, DV, firmware, and physical design teams. Run regression simulations and ensure verification quality through coverage metrics. Automate verification flows and improve efficiency using scripting language...
Posted 1 month ago
6.0 - 8.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Lead Functional Verification Engineer Experience : 6+ Years Location : Bangalore Job Description: Lead verification activities for complex CPU cores, memory subsystems, and high-speed PCIe IPs. Define verification strategy, test plan, and coverage goals based on architecture and spec reviews. Build and maintain advanced UVM-based testbenches for block and subsystem-level verification. Develop reusable components like drivers, monitors, and scoreboards tailored for CPU/memory/PCIe protocols. Drive constrained-random and directed test development to validate corner cases and protocol compliance. Perform end-to-end data path and coherency checks across memory hierarchies and interfaces. Debug R...
Posted 1 month ago
2.0 - 3.0 years
10 - 12 Lacs
hyderabad
Work from Office
Hi all, We are hiring for the role Designer 2 Experience: 2-3 Years (Btech with 2 Years, Mtech with 1 Years) Location: Hyderabad Notice Period: Immediate - 15 days Skills: • Good knowledge of Basic Analog / Digital concepts . • Good knowledge of Verilog / SV concepts . • Experience in using spice simulation and digital simulation tools like Virtuoso , primesim , Finseim , Hspice, Xcellium, Simvision, Waveview. • Experience in understanding Spice simulation environment/Digital simulation environment, able to debug analog/digital design related issues. • Work experience in co-sim simulation designs is a plus. • Good scripting skills using perl, python is a plus. • Must possess good communicati...
Posted 1 month ago
7.0 - 11.0 years
0 Lacs
karnataka
On-site
Wipro Limited is a leading technology services and consulting company dedicated to developing innovative solutions that cater to the most intricate digital transformation needs of clients. With a vast portfolio of capabilities in consulting, design, engineering, and operations, Wipro assists clients in achieving their most ambitious goals and establishing future-ready, sustainable businesses. The company, with over 230,000 employees and business partners operating in 65 countries, is committed to aiding customers, colleagues, and communities in thriving amidst a constantly changing world. For more information, visit www.wipro.com. As a Lead Design Verification Engineer with at least 7 years ...
Posted 2 months ago
7.0 - 10.0 years
20 - 30 Lacs
bengaluru
Work from Office
We are looking for an experienced SoC Level Verification Engineer with 7+ years of relevant experience. Key Responsibilities: Perform SoC level verification using C + UVM based test cases Write test cases and debug for ARM M-core Debugging using disassembly, tarmac, and waveform Work with Cadence and Synopsys VIP for SoC level validation Handle DMA, Interrupts, Cache, and Interconnect verification Work on peripheral protocols (SPI, I2C, I3C, CAN, LIN preferred) Required Skills: Strong ARM M-core experience SoC level verification expertise Hands-on with UVM test benches and C programming Strong knowledge of AHB, APB protocols Familiar with Cadence simulator, Simvision, and debugging tools
Posted 2 months ago
6.0 - 11.0 years
13 - 18 Lacs
Bengaluru
Work from Office
3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Eth...
Posted 4 months ago
4.0 - 8.0 years
20 - 35 Lacs
Bengaluru
Work from Office
Handson experience of baremetal FW development in Pre Si w/ UVM TB, debugging FW using Verdi/Sim Vision along with RTL,basic signal tracing in Verilog, High-Speed Serial I/F for 2yrs : UCIe, PCIe, CXL, HBM, Qlink (Qualcomm), DigRF (MIPI)
Posted 4 months ago
4.0 - 7.0 years
6 - 9 Lacs
Hyderabad
Work from Office
Responsibilities Design and maintain standard cells for new products based on new technology. Characterize the performance of standard cells and optimize the standard cell design and layout. Characterization and modeling of Standard Cell and semi-Custom cells to provide timing/power model for verification. Quality Analysis of characterized liberty models in terms of Timing, Power and Functionality. Closely collaborate with DTCO team to work on stdcells architecture for emerging technologies. Develop automation test bench/flow/tools to improve the work efficiency and help data analysis. Co-work with international colleagues on developing new verification flows to take on the challenges in DRA...
Posted 5 months ago
10.0 - 15.0 years
25 - 30 Lacs
bengaluru
Work from Office
We are hiring DV Contract Engineers with 10+ years of experience in UVM-based testbenches, netlist/gate-level simulations, and datapath blocks. Strong expertise in Cadence tools (Xcelium/Simvision) and scripting (Python/Shell) required. Required Candidate profile Experienced DV engineer with 10+ years in verification, UVM testbench, Cadence tools (Xcelium/Simvision), netlist & gate-level simulations, coverage closure, debugging, and scripting.
Posted Date not available
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