9 Simvision Jobs

Key Responsibilities: Develop and execute verification test plans based on design specifications. Create constrained-random and directed testbenches using SystemVerilog/UVM. Develop functional coverage models and drive coverage closure. Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues. Perform block-level and/or SoC-level verification. Integrate and verify 3rd-party IPs and custom IPs in subsystem and full-chip environments. Collaborate with RTL, DFT, DV, firmware, and physical design teams. Run regression simulations and ensure verification quality through coverage metrics. Automate verification flows and improve efficiency using scripting language...

Lead Functional Verification Engineer Experience : 6+ Years Location : Bangalore Job Description: Lead verification activities for complex CPU cores, memory subsystems, and high-speed PCIe IPs. Define verification strategy, test plan, and coverage goals based on architecture and spec reviews. Build and maintain advanced UVM-based testbenches for block and subsystem-level verification. Develop reusable components like drivers, monitors, and scoreboards tailored for CPU/memory/PCIe protocols. Drive constrained-random and directed test development to validate corner cases and protocol compliance. Perform end-to-end data path and coherency checks across memory hierarchies and interfaces. Debug R...

Hi all, We are hiring for the role Designer 2 Experience: 2-3 Years (Btech with 2 Years, Mtech with 1 Years) Location: Hyderabad Notice Period: Immediate - 15 days Skills: • Good knowledge of Basic Analog / Digital concepts . • Good knowledge of Verilog / SV concepts . • Experience in using spice simulation and digital simulation tools like Virtuoso , primesim , Finseim , Hspice, Xcellium, Simvision, Waveview. • Experience in understanding Spice simulation environment/Digital simulation environment, able to debug analog/digital design related issues. • Work experience in co-sim simulation designs is a plus. • Good scripting skills using perl, python is a plus. • Must possess good communicati...

Wipro Limited is a leading technology services and consulting company dedicated to developing innovative solutions that cater to the most intricate digital transformation needs of clients. With a vast portfolio of capabilities in consulting, design, engineering, and operations, Wipro assists clients in achieving their most ambitious goals and establishing future-ready, sustainable businesses. The company, with over 230,000 employees and business partners operating in 65 countries, is committed to aiding customers, colleagues, and communities in thriving amidst a constantly changing world. For more information, visit www.wipro.com. As a Lead Design Verification Engineer with at least 7 years ...

We are looking for an experienced SoC Level Verification Engineer with 7+ years of relevant experience. Key Responsibilities: Perform SoC level verification using C + UVM based test cases Write test cases and debug for ARM M-core Debugging using disassembly, tarmac, and waveform Work with Cadence and Synopsys VIP for SoC level validation Handle DMA, Interrupts, Cache, and Interconnect verification Work on peripheral protocols (SPI, I2C, I3C, CAN, LIN preferred) Required Skills: Strong ARM M-core experience SoC level verification expertise Hands-on with UVM test benches and C programming Strong knowledge of AHB, APB protocols Familiar with Cadence simulator, Simvision, and debugging tools

3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Eth...

Handson experience of baremetal FW development in Pre Si w/ UVM TB, debugging FW using Verdi/Sim Vision along with RTL,basic signal tracing in Verilog, High-Speed Serial I/F for 2yrs : UCIe, PCIe, CXL, HBM, Qlink (Qualcomm), DigRF (MIPI)

Responsibilities Design and maintain standard cells for new products based on new technology. Characterize the performance of standard cells and optimize the standard cell design and layout. Characterization and modeling of Standard Cell and semi-Custom cells to provide timing/power model for verification. Quality Analysis of characterized liberty models in terms of Timing, Power and Functionality. Closely collaborate with DTCO team to work on stdcells architecture for emerging technologies. Develop automation test bench/flow/tools to improve the work efficiency and help data analysis. Co-work with international colleagues on developing new verification flows to take on the challenges in DRA...

We are hiring DV Contract Engineers with 10+ years of experience in UVM-based testbenches, netlist/gate-level simulations, and datapath blocks. Strong expertise in Cadence tools (Xcelium/Simvision) and scripting (Python/Shell) required. Required Candidate profile Experienced DV engineer with 10+ years in verification, UVM testbench, Cadence tools (Xcelium/Simvision), netlist & gate-level simulations, coverage closure, debugging, and scripting.