DFT Manager

About Tessolve

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up and spec to product. With 3200+ employees worldwide, Tessolve delivers a one-stop solution with advanced silicon and system testing labs. We offer Turnkey ASIC Solutions from design to packaged parts, leveraging strong ecosystem partnerships with EDA, IP, and foundry vendors. Our integrated front-end and backend expertise reduces design risks and accelerates time-to-market.

Our R&D centers of excellence focus on emerging technologies such as 5G, mmWave, Silicon Photonics, HSIO, HBM/HPI, and System-Level Test. Tessolve also delivers end-to-end embedded product design services under an ODM model for Avionics, Automotive, Industrial, and Medical applications.

Tessolve’s clientele includes 9 of the top 10 semiconductor companies, along with Tier-1 clients, start-ups, and government entities. We have a global presence in 12+ countries, with advanced test labs in India, Singapore, Malaysia, Austin, and San Jose.

For more details, visit www.tessolve.com

Position Overview

DFT (Design for Test) Manager

Key Responsibilities

• Lead and manage a team of DFT engineers across multiple projects.
• Define and drive DFT strategy, methodology, and execution for SoC and ASIC programs.
• Work closely with design, verification, and physical design teams to ensure seamless DFT integration.
• Plan and track project schedules, resource allocation, and deliverables to meet customer timelines.
• Provide technical guidance and mentorship to team members on scan, MBIST, JTAG, ATPG, and post-silicon validation.
• Review DFT insertion, coverage analysis, and simulation results to ensure high-quality deliverables.
• Interface with customers to understand requirements, propose solutions, and present project status.
• Drive continuous improvement in DFT flows, automation, and efficiency across projects.

Required Skills and Experience

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field.

• 10+ years

  of hands-on DFT experience, with at least

  2–3 years in a leadership/managerial role.

• Strong expertise in:
• Scan insertion, ATPG, MBIST, and JTAG.
• Tools such as Synopsys DFT Compiler, Tessent, Modus, and Tetramax.
• Fault coverage analysis and pattern generation for high-quality silicon testing.
• Experience with hierarchical DFT flows and handling large SoCs.
• Strong communication, leadership, and cross-functional collaboration skills.
• Customer-facing experience and ability to handle global project engagements preferred.