DFT Manager

Role & responsibilities

Preferred candidate profile

The candidate is expected to have clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts. 

He/she must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys. 

Must have worked on zero delay as well as SDF Timing Simulations and must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium. 

Should have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques. 

Should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug using shmoo plots and graphs. 

Should have experience of providing test mode timing constraints to STA and PD teams. Additional knowledge of Perl/tcl scripting will be an advantage.

Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.

Knowledge on SSN Scan and hand-on implementation knowledge of the same on 2.5D/3D/chiplet-based designs will be an added advantage.

Perks and benefits