4 Ssn Jobs

The ideal candidate for this role should possess a Bachelor's or Master's degree or equivalent practical experience along with a minimum of 5 years of experience in Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies. They should have a proven track record in developing DFT specifications and DFT architecture, fault modeling, test standards, and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation, and verification flow. Preferred qualifications for this position include experience with DFT for a subsystem with multiple physical partitions, Internal JTAG (IJTAG) ICL, Procedural Description Language (PDL) terminology, ICL extraction, Instrument Connectivity Language (ICL) modeling with Siemens Tessent Tool, Spyglass-DFT, DFT Scan constraints, and evaluating DFT Static Timing Analysis (STA) paths. Knowledge of coding languages like Perl or Python, as well as familiarity with DFT techniques like SSN and HighBandwidth IJTAG, are also desirable. As a part of the team responsible for developing custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation in products that are loved by millions worldwide, delivering unparalleled performance, efficiency, and integration. Google's mission to organize the world's information and make it universally accessible and useful guides our work, combining the best of Google AI, Software, and Hardware to create radically helpful experiences. In this role, you will collaborate with Design for testing (DFT) engineers, Register-Transfer Level (RTL), Physical Designer Engineers, System on a chip (SoC) DFT, and Product Engineering team. Your responsibilities will include working on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains, writing scripts to automate the DFT flow, developing tests for Production in the Automatic Test Equipment (ATE) flow, and collaborating with the DFT team to deliver two or more Subsystems in a SoC.,

CANDIDATES MUST RESIDE IN CHENNAI AND FLUENT IN ENGLSH Roles & Responsibilities Represent international clients in various B2B and B2C event-based campaigns Engage sales, recruitment, training, and team leadership Manage and mentor team members while growing into a leadership role Oversee a Strategic Business Unit (SBU) and operate as a Business Partner Contact: 81228 19942 | 91502 33357 Preferred Candidate Profile Entrepreneurial mindset with a strong business orientation Confident in public speaking and delivering impactful presentations Thrives in a fast-paced, performance-driven environment Build and scale high-performing teams. Candidates with entrepreneurial experience or leadership roles in college will have an added advantage

The only candidates who can apply are those who currently reside in Chennai. JOB PROFILE : To collaborate with us on a range of business management tasks, such as business development, human resource management, and sales and marketing. Every level of on-the-job training would be provided, and promotions would solely depend on each employee's success. Roles and Responsibilities Using a variety of B-to-B and B-to-event campaigns to represent International Clients Selling, recruiting, and managing a team Leading a team and growing as a leader directing SBU and serving as a business associate Get clients and build relationships with them Increasing sales and customer acquisition Reliable in increasing sales and skilled in providing sales solutions Serving as the client's point of contact for brand development and marketing CONTACT: 9150233357 or 8122819942 IDEAL CANDIDATE PROFILE : Business-minded and entrepreneurial want to own and operate their own company Self-assurance when presenting and speaking in public At ease in a fast-paced, performance-oriented setting It will be advantageous for candidates with leadership experience in college or entrepreneurial backgrounds. Candidates who currently live in Chennai able to associate right away

Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Your role and responsibilities We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design . Experience working with ATE engineers for silicon bring up, silicon debug and validation. . Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.