Job
Description
Manage an ASIC design verification team and/or managers responsible for various processing blocks in a SOC. Drive verification planning and execution, innovative verification methodology development, functional and code coverage closure. Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams Design Verification Engineering Manager Responsibilities: Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's Long Range Plan objectives Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing Build, lead, and support a team of ASIC engineers through hiring, training, and guidance to drive on-time and on-budget product delivery Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs Define, implement and maintain key performance indicators (KPI) for areas of responsibility Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors Support managers supporting design verification team Minimum Qualifications: B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience 12+ years experience in ASIC/SoC design verification 8+ years of experience as a People Manager, leading people managers and senior ICs. Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal Track record of first-pass success in ASIC Development Experience working across multiple projects and adjusting priorities in partnership with stakeholders Experience managing and delivering UVM constrained random test benches Experience with interpreting functional specs and creating comprehensive test plan Experience managing managers who are supporting small/mid size teams Preferred Qualifications: Hands-on experience with complex subsystems like memory, LPDDR, HBM, cache, PCIe, or network-on-chip including performance verification In depth knowledge of at least one of these areas - video coding standards, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework Experience in formal verification techniques and methodologies About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta. Show more Show less
