Design Engineer

Key Responsibilities:

• Perform

  timing, power, and signal integrity characterization

  of standard cells across different PVT corners.
• Generate

  Liberty (.lib), CCS, ECSM, and other timing/power models

  used by synthesis and place & route tools.
• Develop and validate models for

  dynamic power, leakage power, and noise

  .
• Set up and run

  characterization flows

  using tools such as Synopsys Liberate, Cadence Tempus/Modgen, or equivalent.
• Automate workflows using

  scripts in Python, Perl, Tcl, or Shell

  to improve efficiency and reliability.
• Work with library development and circuit design teams to ensure the quality and completeness of characterized views.
• Debug and resolve

  modeling discrepancies, setup issues, or tool-related bugs

  .
• Participate in

  library QA and validation

  across different design flows and EDA environments.
• Ensure

  consistency between layout, schematic, and extracted views

  for accurate modeling.
• Contribute to

  documentation, release management, and customer support

  as needed.

Required Skills & Experience:

• Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering.
• 3–10 years of hands-on experience in

  standard cell characterization

  .
• Strong understanding of

  CMOS device physics, STA fundamentals, and signal integrity

  .
• Proficiency in

  Liberty format, characterization tools

  , and

  SPICE simulation

  .
• Experience with

  EDA tools

  such as Synopsys Liberate, PrimeTime, Cadence Tempus, HSPICE, Spectre, etc.
• Familiarity with

  advanced nodes

  (7nm, 5nm, 3nm, etc.) and

  FinFET

  technologies.
• Solid scripting experience in

  Python, Tcl, Perl, or Shell

  for automation.
• Good understanding of

  PVT variations, voltage scaling, and multi-corner modeling

  .