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Associate I - VLSI

0 years

0 Lacs

bengaluru karnataka india

Posted:18 hours ago| Platform: Linkedin logo

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Skills Required

design verification dft circuit layout synthesis checks support metrics integration spec documentation teamwork creativity training programming verilog vhdl perl tcl cadence synopsys icc ip architecture test usb ethernet extraction technology communication reasoning flow library timing power compiler analysis scripting python automation recording

Work Mode

On-site

Job Type

Full Time

Job Description

Role Description

Role Proficiency:Works under supervision and guidance to execute internal tasks in any field of VLSI Frontend Backend or Analog design

Outcomes

  • Works as an individual contributor and on any one task of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
  • Complete the assigned task in the defined domain(s) successfully and on-time with support from other team members and senior engineers
  • Ensure quality delivery as approved by the senior engineer

Measures Of Outcomes

  • Quality –verified using relevant metrics by Lead
  • Timely delivery - verified using relevant metrics by Lead
  • Reduction in cycle time and cost using innovative approaches
  • Number of trainings attended

Outputs Expected

Technical Skills:
  • Build up required technical skills and design knowledge to execute the assigned tasks

Quality Of The Deliverables

  • Clean delivery of the module in-terms of ease in integration at the top level
  • Meeting functional spec / design guidelines at least 80% of the time without deviation or limitation
  • Documentation of tasks and work performed

Timely Delivery

  • Meeting project timelines as set forth by the team lead
  • Help with intermediate tasks delivery with other team members to aid progress

Teamwork

  • Participation in teamwork at the time of need
  • Able to take on additional tasks incase of any team member(s) is not available

Innovation & Creativity

  • Understand how to approach repetitive work by automating tasks saving design cycle time
  • Participation in technical discussion training forum

Skill Examples

  • Languages and Programming skills: System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)
  • EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)
  • Technical Knowledge: (any one)a. Learn to understand IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Theoretical knowledge in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Fair knowledge of Physical Design / Circuit Design / Analog Layout d. Fair understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verification
  • Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below
  • Able to deliver the tasks with quality at least 80 % on-time per quality guidelines and GANTT
  • Good communication skills
  • Good analytical reasoning and problem-solving skills and attention to details
  • Ability to learn new skills in case required technical skills are not present at a level needed to execute the project

Knowledge Examples

  • Basic understanding in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.
    • Understanding of the design flow and methodologies used in the designing
    • Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the manager per skill set

Additional Comments

Job Description: Role and Responsibilities:
  • Experience with at least one characterization tool (SiliconSmart/Liberate) for complete characterization of a library to generate the front end and back end views.
  • Understanding of CCS, ECSM liberty models,LVF, Verilog models, statistical characterization.
  • Understanding of characterization methodologies for combinational, sequential cells and timing, power, capacitance models.
  • Knowledge of cell characterization flows and methodologies, library verification and validation.
  • Familiarity with circuit simulators, liberty syntax, library compiler, design compiler.
  • Basic understanding of static timing analysis and synthesis .
  • Scripting skills with python,shell,tcl. Skill Requirements:
  • Characterization and generation of front end and back end views for standard cell libraries· Custom cell characterization setup and flows· Library verification and validation· Automation for the QA checks, for small tasks in setting up the flows for characterization and QA· Documentation of and recording the issues, debugs, solutions and new/enhanced work flows· Mentor and enhance the skill set of junior team members Good to have: Automation skills like python modules .APL,CCSP.PGV generation flow knowledge Qualifications: B.Tech /B.E/M.Tech/M.E

Skills

Characterization,Static Timing Analysis,Library compiler

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