Job
Description
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. PVT Sensor IP development is a critical offering for process, voltage, temperature, and other monitoring IPs within SOC subsystems. Synopsys is the market leader for these IP developments which are integral parts of Silicon lifecycle monitoring. You Are: As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity and forward-looking project schedules. Your understanding of DV flow, generating test benches, and test cases will be crucial. You have experience with RTL and gate-level SDF-annotated simulations and debug, and may also perform mixed-signal (digital + analog) simulations and debug. Your role will involve interacting with our application engineers and providing guidance to customers, participating in the generation of data books, application notes, and white papers. What You’ll Be Doing: Understanding DV flow and generating test benches and test cases. Performing RTL and gate-level SDF-annotated simulations and debug. Conducting mixed-signal (digital + analog) simulations and debug. Interacting with application engineers and providing customer guidance. Contributing to the generation of data books, application notes, and white papers. Performing physical verification and design rule checks to ensure design integrity and manufacturability. Enhancing quality assurance methodology by adding more quality checks and gating. Supporting internal tools development and automation to improve productivity across ASIC design cycles. Driving automation to enhance IP Quality-Assurance flow and release process. Integrating new features and functionalities into IPQA scripts with the automation team. The Impact You Will Have: Ensure the integrity and manufacturability of designs through rigorous verification and checks. Enhance the efficiency and effectiveness of engineering processes through automation and tool development. Support and guide customers, improving their experience and satisfaction with our products. Contribute to the creation of high-quality documentation that aids in the understanding and use of our IPs. Strengthen the forecasting capabilities of the engineering teams, leading to better project planning and execution. Drive innovation and continuous improvement in IP development and quality assurance processes. What You’ll Need: Bachelor’s or master’s degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views and collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills. Who You Are: A proactive individual with excellent problem-solving and systematic skills. Detail-oriented and capable of working effectively in a team-oriented environment. Adaptable and able to thrive in a fast-paced and dynamic setting. Enthusiastic about continuous learning and technological innovation. Customer-focused with a commitment to delivering high-quality solutions. The Team You’ll Be A Part Of: You will be part of a highly skilled and collaborative engineering team focused on developing leading-edge IPs for the semiconductor industry. This team is dedicated to innovation, quality, and customer satisfaction, working together to push the boundaries of technology and deliver exceptional products. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less
