This position is posted by Jobgether on behalf of Alphawave IP inc. We are currently looking for a Staff Engineer - STA in India.
In this role, you will play a key part in driving timing convergence for complex SoCs, ensuring high performance and reliable tape-outs across advanced technology nodes. You will collaborate with cross-functional teams, contribute to methodology development, and manage timing closure for multi-mode and multi-corner designs. This position offers the opportunity to lead impactful engineering projects while working in a flexible, collaborative environment that values innovation, precision, and professional growth.
Accountabilities
As a Staff Engineer - STA, you will:
- Lead static timing analysis (STA) setup, reviews, and sign-off for multi-mode, multi-corner, and multi-voltage domain designs
- Develop and maintain constraints for block and SoC hierarchical designs across multiple modes
- Drive timing closure at the full-chip level, supporting physical design teams on block and subsystem convergence
- Collaborate with design, DFT, IP, and PD teams to resolve constraint conflicts and ensure robust timing strategies
- Guide clock tree synthesis (CTS) methodologies and provide strategic input to implementation teams
- Manage ECO generation and implementation methodologies to achieve timing closure
- Support gate-level simulations and verification enablement
- Create automation scripts to enhance STA methodologies and processes
Requirements
To be successful in this role, you should bring:
- 7-14 years of experience in synthesis and STA for full-chip sign-off and tape-outs
- Hands-on expertise with both block-level and full-chip timing constraints for hierarchical designs
- Strong knowledge of DFT constraints and ASIC physical design implications on timing
- Experience with Synopsys/Cadence tools, advanced node technologies, and variation/aging-aware design sign-off
- Solid understanding of timing budgets, CTS methodologies, and power/timing/area trade-offs
- Proficiency in scripting languages such as Perl, TCL, or Python
- Familiarity with multi-voltage designs using CPF/UPF and power analysis with PTPX
- Knowledge of VHDL/Verilog constructs, RTL debugging, and IP-level verification
- Excellent communication skills, with the ability to explain complex technical issues clearly
- A collaborative mindset with enthusiasm for problem-solving and teamwork
Benefits
You will enjoy a comprehensive benefits package designed to support your well-being and career growth:
- Competitive compensation package
- Restricted Stock Units (RSUs)
- Opportunities for advanced education and access to eLearning providers
- Comprehensive medical insurance and wellness benefits
- Educational assistance and loan support programs
- Office-provided lunch and snacks
- Inclusive and flexible work environment supporting both personal and professional success
Jobgether is a Talent Matching Platform that partners with companies worldwide to efficiently connect top talent with the right opportunities through AI-driven job matching.
When you apply, your profile goes through our AI-powered screening process designed to identify top talent efficiently and fairly.🔍 Our AI evaluates your CV and LinkedIn profile thoroughly, analyzing your skills, experience and achievements.📊 It compares your profile to the job's core requirements and past success factors to determine your match score.🎯 Based on this analysis, we automatically shortlist the 3 candidates with the highest match to the role.🧠 When necessary, our human team may perform an additional manual review to ensure no strong profile is missed.The process is transparent, skills-based, and free of bias — focusing solely on your fit for the role. Once the shortlist is completed, we share it directly with the company that owns the job opening. The final decision and next steps (such as interviews or additional assessments) are then made by their internal hiring team.Thank you for your interest!
