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Sourceright Technologies
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Senior STA Engineer

Senior STA Engineer

Sourceright Technologies

5 - 10 years

|

20 - 25 Lacs

Posted:-1 days ago| Platform:

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Skills Required

physical design scanning icc floorplan routing drc asic synthesis perl tcl synthesis cmos sta primetime lvs timing analysis verilog asic design physical verification floor planning signal integrity timing closure pnr placement synopsys vlsi

Work Mode

Work from Office

Job Type

Full Time

Job Description

Timing analysis, validation and debug across multiple PVT conditions using Tempus.
Familiar with Tempus DMMMC flow for STA and logical/physical aware ECO flows focusing timing and leakage optimization.
Peripheral timing checks.
STA setup, convergence, reviews and signoff for multi-mode (func/scan/atspeed/atspeed exceptions), multi-voltage domain designs.
Review of Unconstrained endpoints and check timing reports.
Proficient in STA and timing methodologies with good understanding of noise, crosstalk, and OCV effects.
Should have worked on both block level and full chip timing closure in 16nm, 5nm and below.
Additionally, closely interact with designers/synthesis/PNR team to provide the feedback to ensure smooth timing closure.

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Sourceright Technologies

Technology / Human Resources

Silicon Valley

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