Preferred candidate profile Technical Skills Languages : SystemVerilog, Verilog, C/C++ (basic) Verification Methodologies : UVM (Universal Verification Methodology), Assertion-Based Verification (SVA) Protocols : Experience with one or more of the following: PCIe Gen5/6 AXI4, AHB, APB DDR4/DDR5 USB 3.1/3.2 Ethernet, MIPI, or NVMe Tools : Synopsys VCS, Cadence Xcelium, Mentor Questa, Verdi, SimVision Debug : Waveform debugging (Verdi/DVE), assertions, log analysis
Role & responsibilities : Lead /manage SoC/IP/Package-level verification projects, ensuring quality and timely delivery. Architect and drive UVM-based verification environments and methodologies. Define verification strategies, develop test plans, and ensure signoff criteria (functional & code coverage, power analysis, GLS) are met. Collaborate cross-functionally with design, DFT, physical design, and software teams to ensure robust verification coverage and silicon success. Manage team deliverables, mentor junior engineers, and provide technical guidance. Interface with stakeholders for project scoping, scheduling, and resource allocation. Drive silicon debug, pattern verification, and post-silicon validation efforts. Ensure alignment with industry best practices, including low power verification (PTPX, Spyglass) and high-speed interface validation. Preferred candidate profile 7+ years of experience in ASIC/SoC verification . Proven track record of leading teams to successful silicon tape-outs . Hands-on expertise in UVM, SystemVerilog, Assertions, functional and code coverage closure. Strong understanding of SoC architecture with ARM cores (e.g., Cortex-M4, M6, ARM926EJ-S). Experience in verification of high-speed protocols (SATA, PCIe), AMBA protocols (AXI, AHB, APB), and standard interfaces.. Excellent people management, project planning, and stakeholder communication skills.
Role & responsibilities Develop, validate, and maintain STA constraints (SDC) for multiple design modes and corners (functional, test, scan, BIST, low power, etc.). Own DFT timing constraints (scan shift, capture, at-speed test, boundary scan, MBIST, LBIST, JTAG). Collaborate with DFT and Physical Design teams to ensure test structures meet timing closure requirements. Work with synthesis, P&R, and STA teams to merge functional and test-mode constraints consistently. Debug timing violations across functional and DFT modes, and propose fixes (false paths, multicycle paths, case analysis, test clocks). Ensure SDC quality by writing scripts/checkers for constraint consistency, redundancy, and coverage. Interface with ATPG teams to validate scan patterns with timing intent. Participate in signoff STA , including test modes, to ensure tapeout quality. Desired Skills: Strong expertise in STA constraint development and debugging. Hands-on experience with SDC, DFT constraints, and signoff STA tools . Good scripting skills for automation and validation. Excellent collaboration skills across cross-functional teams.