Verification Engineer : Available To Join in 45 Days or Less

4 - 9 years

10 - 20 Lacs

Posted:2 months ago| Platform: Naukri logo

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Skills Required

Work Mode

Work from Office

Job Type

Full Time

Job Description

Preferred candidate profile Technical Skills Languages : SystemVerilog, Verilog, C/C++ (basic) Verification Methodologies : UVM (Universal Verification Methodology), Assertion-Based Verification (SVA) Protocols : Experience with one or more of the following: PCIe Gen5/6 AXI4, AHB, APB DDR4/DDR5 USB 3.1/3.2 Ethernet, MIPI, or NVMe Tools : Synopsys VCS, Cadence Xcelium, Mentor Questa, Verdi, SimVision Debug : Waveform debugging (Verdi/DVE), assertions, log analysis

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