- Senior Standard Cell Layout Engineer
- Standard Cell Layout Designer
- Digital Layout Engineer
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are an experienced and highly motivated professional with a robust technical background in standard cells layout design. Your passion for excellence and precision drives you to create layouts that set the standard for quality and manufacturability. You thrive in collaborative, cross-functional environments, seamlessly working with circuit designers, verification engineers, and other stakeholders to deliver optimized layout solutions. Your expertise in industry-leading EDA tools—such as Cadence Virtuoso or Synopsys Custom Compiler—enables you to tackle complex digital circuit layouts with efficiency and accuracy.Your systematic approach and strong problem-solving skills allow you to navigate technical challenges with ease, always seeking innovative ways to enhance design methodologies and best practices. You are deeply familiar with physical verification processes and design rule checks, ensuring that every layout you deliver meets stringent quality and manufacturability standards. Your curiosity and commitment to lifelong learning keep you updated on the latest advancements in standard cell layout design, making you an invaluable resource for your team. You communicate effectively, embrace feedback, and are eager to contribute to a culture of continuous improvement and shared success.
What You’ll Be Doing:
- Collaborate with cross-functional teams to develop and implement layout designs for digital circuits, ensuring alignment with project goals and timelines.
- Create and optimize complex standard cell layouts using industry-standard EDA tools such as Cadence Virtuoso or Synopsys Custom Compiler.
- Perform thorough physical verification and design rule checks (DRC/LVS) to guarantee design integrity and manufacturability.
- Work closely with circuit designers to understand design specifications, constraints, and performance targets, translating them into robust layouts.
- Contribute to the development, documentation, and refinement of layout design methodologies, flows, and best practices within the team.
- Remain up to date with industry trends, emerging technologies, and advancements in standard cell layout design, sharing knowledge with peers.
The Impact You Will Have:
- Deliver high-quality layout designs that form the foundation of Logic Libraries IP development, essential for advanced SOC subsystems.
- Drive innovation in layout design methodologies, contributing to Synopsys’ leadership in the industry.
- Ensure that all designs meet or exceed manufacturability and reliability standards, reducing risk and time-to-market for key products.
- Collaborate effectively with circuit designers and verification teams to meet challenging design specifications and project milestones.
- Contribute to the overall success and reputation of the Logic Libraries IP group through your technical excellence and teamwork.
- Mentor and support junior team members, fostering a culture of knowledge-sharing and continuous improvement.
What You’ll Need:
- Bachelor’s or master’s degree in electronics engineering or a related field.
- Minimum2 years of hands-on experience in standard cells layout design for digital circuits.
- Proficiency with industry-standard EDA tools, including Cadence Virtuoso or Synopsys Custom Compiler.
- Deep knowledge of layout design methods, techniques, and methodologies for high-performance and robust standard cells.
- Experience with physical verification tools such as ICC2, including DRC and LVS checks.
- Strong analytical and systematic problem-solving skills, with a detail-oriented mindset.
- Ability to work effectively in a collaborative, team-driven environment.
- Excellent communication and interpersonal skills, with a willingness to learn and share knowledge.
Who You Are:
- A collaborative team player who values open communication and shared goals.
- Detail-oriented, with a commitment to delivering high-quality and reliable work.
- Curious and proactive, embracing continuous learning and professional development.
- Adaptable and resilient in the face of technical challenges and evolving requirements.
- Passionate about innovation, with a drive to improve processes and methodologies.
- Self-motivated, organized, and able to manage multiple priorities in a fast-paced environment.
The Team You’ll Be A Part Of:
You’ll join a dynamic and supportive Logic Libraries IP group focused on developing state-of-the-art standard cell libraries for advanced SOC subsystems. Our team thrives on collaboration, innovation, and technical excellence. We value diverse perspectives and foster an inclusive environment where every member’s contributions are recognized and celebrated. Together, we drive the success of Synopsys’ IP solutions, setting industry benchmarks and enabling our customers to achieve next-generation performance.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
