RTL Engineer

What you’ll do:

· Own and bring up emulation cutdowns cutdowns for large SoC and IP blocks to improve emulation performance and turnaround time.

· Adapt and port test benches to run efficiently on hardware emulation platforms.

· Debug and resolve issues related to AVIPs and transactors within the emulation environment.

· Lead the bring-up and setup of emulation platforms (Palladium, Zebu) to ensure readiness for verification runs.

· Collaborate closely with RTL designers, verification, and emulation infrastructure teams to ensure high coverage and quality.

· Troubleshoot test failures on emulators and provide actionable feedback to design and DV teams.

· Release validated emulation cutdowns and test benches to software, DV, or STA teams.

Who you are:

· 6+ Years of experience in RTL design/verification and hardware emulation

· Hands-on experience with Cadence Palladium and/or Synopsys Zebu emulators.

· Strong skills in debugging and developing AVIPs and transactors.

· Proficiency in SystemVerilog, UVM, and scripting languages such as Python, Perl, and Shell.

· Solid understanding of SoC architecture, verification methodologies, and hardware/software co-debugging.

· Experience with waveform analysis tools (Verdi, DVE).

· Ability to analyze, reduce, and optimize test cases while maintaining coverage and validity.

· Excellent problem-solving and communication skills, with a collaborative mindset.

Job Type: Full-time

Pay: ₹4,000,000.00 - ₹6,000,000.00 per year

Application Question(s):

• Notice Period?

Experience:

• RTL Engineer: 6 years (Required)
• RTL design/verification and hardware emulation: 4 years (Required)
• Palladium and/or Synopsys Zebu emulators: 3 years (Required)
• skills in debugging and developing AVIPs and transactors.: 4 years (Required)

Location:

• Bangalore, Karnataka (Preferred)

Work Location: In person