Drive full-chip DRC/LVS signoff using ICV
Debug and close DRC/LVS violations across block-level and hierarchical boundaries and guide the team on fixing them.
Execute ERC, PERC, antenna checks, metal density, and advanced-node reliability rules in process node 22nm, 16nm or below.
Own rule-deck interpretation and collaborate with foundries to resolve tapeout waivers and other DRC issues.
Interface with tool vendors to resolve tool issues on an independent basis
Explore and assess new tool features and automate them into the flow
Perform layout audits and ensure adherence to technology and process rules. IR-Drop / EM Signoff
Lead static, dynamic IR-drop, EM and in-rush current analyses for full-chip and block-level designs using Ansys RedHawk.
Identify IR-drop hotspots, root-cause issues, and guide the team on fixing them.
Perform EM signoff and drive fixes through layout and power-grid improvements.
Collaborate with PD, STA, and RTL teams to optimize power integrity and timing margins.
Work with power architects to validate power-grid requirements, power domains, and UPF-based flows.
Work with the tool vendors to debug and resolve tool issues
Explore and assess new tool features and automate them into the flow

Team Collaboration

Partner with STA engineers to ensure timing and IR-drop closure alignment.
Interface with foundries for rule clarifications and signoff deviations/waivers.
Provide design reviews and best-practice guidance to the team on advanded tech nodes Automation & Methodology
Develop scripts (Tcl/Perl/Python) to automate PV/IR flows and improve efficiency where required.
Develop automation to perform layout edits and custom reporting in ICV Workbench
Good understanding of grid configuration for efficient use of machines and faster turn-around of jobs.
Contribute to methodology enhancements and signoff flow improvements.
Build dashboards and reports for PV/IR status tracking and tapeout readiness.

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