1400 Jobs in Greater Hyderabad Area - Page 10

About the Role We are looking for a Generative AI Engineer with strong software engineering skills and hands-on experience in developing AI-powered applications . This role involves coding AI-driven solutions, developing APIs, integrating models into products, and building scalable AI systems for production use. Key Responsibilities: · Develop AI-driven applications by integrating LLMs and generative models into real-world software solutions. · Design and build APIs for LLMs and GenAI models (FastAPI, Flask, Django). · Write production-ready code to integrate AI features into web applications, chatbots, document processing tools, and recommendation systems. · Fine-tune and optimize LLMs (GPT, LLaMA, Gemini, Claude, Mistral) for performance in real-time applications. · Develop AI-powered chatbots, document extraction tools, and automation systems using LangChain, Haystack, or Semantic Kernel. · Implement vector search using FAISS, ChromaDB, or Pinecone for retrieval-augmented generation (RAG) applications. · Work with databases (PostgreSQL, MongoDB, Redis) to manage AI-driven data workflows. · Build scalable AI microservices and integrate them into enterprise applications . · Collaborate with backend engineers, data engineers, and DevOps teams to ensure seamless deployment of AI models. Required Skills & Qualifications: · Bachelor’s or Master’s in Computer Science, Software Engineering, AI, or related field . · 6+ years of experience in software development, AI engineering, or full-stack AI application development . · Strong Python coding skills with experience in frameworks like FastAPI, Flask, Django. · Hands-on experience developing APIs for AI models and integrating them into real-world applications. · Experience with LLM APIs (OpenAI, Gemini, Claude, Mistral, etc.) and fine-tuning custom models. · Strong knowledge of vector databases (FAISS, ChromaDB, Pinecone) for AI-powered search . · Experience working with WebSockets, asynchronous programming, and RESTful APIs . · Database experience with PostgreSQL, MongoDB, or Redis for AI-driven applications. · Experience with MLOps pipelines (MLflow, Airflow, Prefect) for model retraining and monitoring . Good to have Skills & Qualifications: · Familiarity with containerization (Docker, Kubernetes) and cloud-based AI deployments (AWS, GCP, Azure) . · Basics of probabilistic models, deep learning techniques, NLP, and embeddings .

The role of a Key Accounts Manager - Channel Partner, would involve meeting Channel Partners (CP) daily and getting Referral Customers from Channel Partner. Account management in the designated zone by building a strong network of real estate brokers in an allocated area and developing partnerships with them. Key Responsibilities : • Regular visits to the channel partners, new and old, to build a strong influence over the network. • Ensure a continuous flow of customer database and leads through the help of your channel partners. Ensure the highest level of quality in leads : A high-quality lead can be defined as an Experience Centre Visit or Site Visit for each Customer Lead shared by the Channel Partner. • • Coordinating to ensure that appropriate action has been taken on customer requests. Ensuring engagement through trust, communication, and service offerings of the company Maintaining the brand image of the company by appropriate code of conduct •

Experience : 4.00 + years Salary : USD 3703 / month (based on experience) Expected Notice Period : 15 Days Shift : (GMT+05:30) Asia/Kolkata (IST) Opportunity Type : Remote Placement Type : Full Time Contract for 6 Months(40 hrs a week/160 hrs a month) (*Note: This is a requirement for one of Uplers' client - PT) What do you need for this opportunity? Must have skills required: AML/KYC, Implemented Stripe, Infrastructure-as-code (Terraform, or other compliance-driven, or similar payment flows., Paddle, Pulumi) and secure SDLC practices., sanctions-screening, Experience deploying and operating workloads on Vercel or GCP, Next.js & React, Supabase, PostgreSQL, TypeScript, Node PT is Looking for: Senior / Lead Full-Stack Engineer (AI-Accelerated) Full Time Why this role exists One of our client projects is building a next-generation platform moving from prototype to production release. We need a senior engineer to own the build—shipping features fast, integrating third-party services, hardening for security and compliance. The developer must be comfortable with utilising AI tooling (Bolt, v0, Cursor, Claude Code, GitHub Copilot) into everyday development. We will of course provide all necessary accounts / licensing. What You’ll Do Prototype & core feature delivery Strengthen and extend the existing prototype built with Next.js / React (TypeScript), backed by PostgreSQL / Supabase. Refine onboarding, risk-scoring, case-management, and reporting workflows. Product expansion & integrations Add KYC/AML data sources, payment processing, advanced authentication (MFA, SSO), alert/notification channels, and domain association. Drive end-to-end testing, security controls, and regulated-industry compliance. AI-accelerated engineering Use Cursor, Claude, Copilot, etc. for code generation, test scaffolding, migration scripts, documentation, and quick architectural prototypes. Prototype AI-powered product capabilities (e.g., suspicious-activity insights, natural-language rule builders). Architecture & DevOps Design, deploy, and operate scalable infrastructure—hosting may be on Vercel or Google Cloud Platform (GCP)—with CI/CD, observability, performance tuning, and cost optimisation. Technical leadership & collaboration Partner with the Solution Architect / Product Manager on backlog grooming, workshops, and agile ceremonies. Establish coding standards, lead code reviews, mentor teammates, and foster a product-engineering mindset. Must-have Qualifications 4+ years professional software development, including 2 + years in a senior or lead capacity. Production expertise with Next.js & React, strict TypeScript, and modern state-management patterns. Deep SQL & schema design on PostgreSQL plus hands-on Supabase (RLS, Functions, Auth). Experience deploying and operating workloads on Vercel or GCP . Daily user of Cursor, Claude (Code), GitHub Copilot or comparable AI coding assistants. Track record of shipping in agile, product-led startup environments—balancing speed with maintainability. Excellent written & spoken English for crisp specs, PRs, and stakeholder communication. Nice-to-haves AML/KYC, Sanctions-screening, Or Other Compliance-driven Systems Experience. Implemented Stripe, Paddle, or similar payment flows. Built notification pipelines with Twilio, OneSignal, or equivalent. Familiarity with LLM fine-tuning / retrieval-augmented generation and vector databases. Infrastructure-as-code (Terraform, Pulumi) and secure SDLC practices. Success measures Prototype evolved into a feature-complete, user-validated application. Integrations, payments, and advanced auth live in staging and ready for production. Cycle time and defect rate reduced through AI-assisted workflows we will develop Comprehensive test coverage, security posture, and monitoring dashboards established How to apply for this opportunity? Step 1: Click On Apply! And Register or Login on our portal. Step 2: Complete the Screening Form & Upload updated Resume Step 3: Increase your chances to get shortlisted & meet the client for the Interview! About Uplers: Our goal is to make hiring reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant contractual onsite opportunities and progress in their career. We will support any grievances or challenges you may face during the engagement. (Note: There are many more opportunities apart from this on the portal. Depending on the assessments you clear, you can apply for them as well). So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

Experience : 5.00 + years Salary : USD 2500-3000 / year (based on experience) Expected Notice Period : 15 Days Shift : (GMT+01:00) Africa/Algiers (CET) Opportunity Type : Remote Placement Type : Full Time Permanent position(Payroll and Compliance to be managed by: Insource India or Uplers) (*Note: This is a requirement for one of Uplers' client - Global company available in 185+ countries) What do you need for this opportunity? Must have skills required: isomorphic React, ES6+ syntax, React Libraries, HTML / CSS, JavaScript, React Js Global company available in 185+ countries is Looking for: Front-End Engineer Remote Company empowers employers to be free from geographical boundaries when accessing talent, allowing employees to pursue opportunities wherever they may exist. We are on a mission to be the FIRST to truly revolutionise the industry and be a generational company. Our platform offers a full-range people management tool, employee benefits like health insurance, and financial benefits, and enabling clients to hire anyone from anywhere with one click. Company manages employees and contractors for Fortune 500 companies (e.g., Microsoft, Mastercard) and the best startups worldwide (e.g., TransferGo). We are a small but strong team of 100+ people (and growing) hyper-focussed on delivering a world-class platform and unparalleled service with our industry-leading partnerships. To help accelerate our growth and pace of delivery, we are looking for talented Front-End Engineers to help spearhead the overall look and feel of our features and services. We are seeking a talented Front-End Engineer specializing in React.js to join our growing team. The ideal candidate will have a strong foundation in front-end technologies and a proven track record of building scalable, responsive, and user-friendly web applications. As part of our agile development team, you will play a crucial role in the entire application lifecycle, from concept to deployment, driving innovation and ensuring the highest quality standards. What you'll be doing: Design, develop, and optimize front-end features for web applications using React.js and other modern JavaScript frameworks and libraries. Collaborate with UI/UX designers to translate designs and wireframes into high-quality code, ensuring visual and functional consistency across all web and mobile platforms. Implement responsive design principles to ensure that our applications render well across a variety of devices and window sizes. Participate in code reviews, contributing to the continuous improvement of product quality and team productivity. Integrate with RESTful APIs and back-end services, understanding the full web technology stack. Write clean, maintainable, and efficient code; adhering to best practices in web development. Stay abreast of emerging technologies and industry trends, applying them to operations and activities to drive innovation. Assist in the estimation of tasks, identify potential roadblocks, and contribute to project planning and sprint iterations. What you’ll need: Bachelor's degree in Computer Science, Engineering, or a related field. 5+ years of professional experience in front-end development, with a strong focus on React.js. Proficient understanding of web markup, including HTML5 and CSS3. Solid experience with JavaScript, including ES6+ syntax, and with popular React libraries (Redux, React Query, etc.) Knowledge of isomorphic React is a plus. A knack for benchmarking and optimization. Familiarity with code versioning tools, such as Git. Excellent problem-solving skills and the ability to think analytically. Strong communication and teamwork skills, with a positive attitude and a commitment to professional development. Why work here? Startup environment. company is an early-stage start-up. You have a voice and can influence and grow rapidly. Build & Scale From Scratch. Experience hyper-growth scale and help us build a great team of professionals worldwide that can help us achieve this ambitious vision. Work for a Market Leader. Scale a project that counts market-leading companies like Microsoft, Mastercard, and more as happy customers. Compensation and perks are great! Competitive compensation. Work equipment of your choice 100% remote work. PTO regulated by local statutory. Culture. We lead with respect, kindness, and the right to fail. We value hard yet smart work. Diversity and inclusion are part of our DNA. As we grow and evolve, we welcome your input to help us define our culture further. How to apply for this opportunity? Step 1: Click On Apply! And Register or Login on our portal. Step 2: Complete the Screening Form & Upload updated Resume Step 3: Increase your chances to get shortlisted & meet the client for the Interview! About Uplers: Our goal is to make hiring reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant contractual onsite opportunities and progress in their career. We will support any grievances or challenges you may face during the engagement. (Note: There are many more opportunities apart from this on the portal. Depending on the assessments you clear, you can apply for them as well). So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

A Day in the Life of a Field Executive 🏃‍♂️ What You’ll Be Doing Daily: 📄 Show the ShinePoints brochure and pitch the software to all types of retail shops (grocery, medical, fashion, electronics, etc.). 🏪 Visit 10–15 stores per day in your assigned city or area. 🕒 Spend 5–10 minutes explaining the benefits to the shopkeeper and 2 minutes onboarding them into the free trial. 🧑‍💻 Create a login instantly using your mobile/tablet to activate the free 1-month offer. 🔁 Revisit the shop after 1 month to collect feedback and convert them to a ₹999 annual subscription. 🤝 Ask for referrals from happy clients to quickly grow your network and close more deals. 🎯 Achieve and overachieve your target of 50 store tie-ups per month to unlock variable incentives. 📱 Update your daily report via mobile — no office visit needed.Eligibility Criteria: ✔ Education: Minimum 12th Pass (Graduates preferred) ✔ Experience: Freshers or candidates with less than 6 months of experience can apply ✔ Languages: Good communication skills in regional language and basic English Salary: 💰 12th Pass: ₹3 LPA CTC (Approx. ₹25,000 per month take-home) + Incentives 💰 Graduate: ₹3.8 LPA CTC (Approx. ₹31,000 per month take-home) + Incentives Work Mode & Timings: 📍 Location: Any area in your assigned city 🏢 Work Mode: Field work, no need to come to the office daily ⏰ Timings: 9 AM – 5 PM 📅 Working Days: Monday to Saturday (6 days/week) Process: 1 Month Probation followed by Full time employment Work Mode & Timings:

www.omnidesigntech.com Principal Analog/Mixed-Signal IC Design Engineer US Based Start-up founded by Industry Veterans who have PhDs from MIT and Stanford Location: Bangalore / Hyderabad Senior Analog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will do high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications 5+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc. Must have a track record of successfully taking designs to production Must have experience with evaluating silicon on bench and familiarity with standard lab equipment Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools MATLAB understanding would be preferred but not mandatory Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes Must be able to work independently, create and adhere to schedules Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations Should be able to seek help proactively as well as share and pass on knowledge . we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Senior Analog Design Engineer Top100 Global Semiconductor Organization HQ in California. Revenue over 200 Million USD Location: Bangalore Job Summary The Analog Engineer of Circuit Design Engineeri . The ideal candidate is a highly motivated, self-starting, leader . The position will have significant exposure with opportunity for career growth. It is not necessary to meet all job requirements to be a qualified candidate for the position. Responsibilities: Provide wide and sharp technical expertise, and quickly understand new and unfamiliar technical subjects and form opinions/strategies to resolve challenges and/or recommend and implement on new opportunities. Collaborate with Systems Engineering, Test Engineering, and Applications teams to design chips with DFT, DFM, achieve rapid silicon bring-up and fast time-to-production release. Partner with Customers, Marketing, and Sales to define products, roadmaps, and schedules to target and win key designs. Qualifications & Requirements: MS Degree in Electrical Engineering or equivalent field, PhD preferred. Minimum 5-10 years industry experience in custom Analog IC circuit design, developing: PLL and Oscillators and nice to have experience in other analog building blocks like…. Frequency synthesis architecture/circuits, Voltage References, bias circuits, Switched capacitor or sampling circuits, high performance ADC and DACs, Linear regulators. Temperature Sensors, high-speed op amps Proven track record of designing and producing (in high volume) profitable complex mixed-signal chips. Desired Characteristics & Attributes: Excellent analytical and problem-solving skills required. Excellent written and verbal communication skills required. Ability to work well with others in a fast-paced collaborative team environment. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.omnidesigntech.com Principal Analog/Mixed-Signal IC Design Engineer US Based Start-up founded by Industry Veterans who have PhDs from MIT and Stanford Location: Bangalore / Hyderabad Principal Analog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will do high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications 8+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc. Must have a track record of successfully taking designs to production Must have experience with evaluating silicon on bench and familiarity with standard lab equipment Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools MATLAB understanding would be preferred but not mandatory Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes Must be able to work independently, create and adhere to schedules Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations Should be able to seek help proactively as well as share and pass on knowledge . we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Analog Design Manager Top100 Global Semiconductor Organization HQ in California. Revenue over 200 Million USD Location: Bangalore Job Summary The Analog Manager of Circuit Design Engineering will be responsible for building and leading the Indian through the development . The ideal candidate is a highly motivated, self-starting, leader adept at driving fast-moving design engineering teams and possessing excellent technical, managerial, and communications skills. The position will have significant exposure with opportunity for career growth. It is not necessary to meet all job requirements to be a qualified candidate for the position. Responsibilities: Recruit, build, and motivate world-class engineering teams. Encourage, practice, and enhance our culture for creating pleasant and highly efficient work environment. Lead a cross-functional IC Design team consisting of Analog, Mixed-Signal, Digital, and Layout engineers, to develop solutions that address high-performance and ultra-low power applications. Provide wide and sharp technical expertise, and quickly understand new and unfamiliar technical subjects and form opinions/strategies to resolve challenges and/or recommend and implement on new opportunities. Identify products and processes shortcomings and constraints. Propose and implement optimal procedures that resolve problems suited for the stage of the company and its resources. Make products level decisions, including testability, manufacturing, cost, applications, and product support features/consideration. Collaborate with Systems Engineering, Test Engineering, and Applications teams to design chips with DFT, DFM, achieve rapid silicon bring-up and fast time-to-production release. Partner with Customers, Marketing, and Sales to define products, roadmaps, and schedules to target and win key designs. Manage engineers to accomplish customer, schedule, and budget goals. Drive other projects as needed by management or as business needs change. Qualifications & Requirements: MS Degree in Electrical Engineering or equivalent field, PhD preferred. Minimum 10-15 years industry experience in custom Analog IC circuit design, developing: PLL and Oscillators and nice to have experience in other analog building blocks like…. Frequency synthesis architecture/circuits, Voltage References, bias circuits, Switched capacitor or sampling circuits, high performance ADC and DACs, Linear regulators. Temperature Sensors, high-speed op amps Minimum 3 years proven experience in a similar leadership role Proven track record of designing and producing (in high volume) profitable complex mixed-signal chips. Track record of planning and execution from Product Concept through Design Implementation, Tape-out, Sampling and production release. Ability to execute methodically to deliver projects and products. Proven track record at each stage of the following: Architecture development and feasibility studies. Writing specifications at both system and block level. Design partitioning for noise / power / area budgeting. Knowledge of ultra-low phase-noise design, power supply noise considerations, device matching, parasitic extraction, signal integrity, ESD. Supervision of layout and editing critical blocks. Chip level design and verification of complex mixed-signal chips. Chip validation, characterization, qualification, release to production. Ability to cross-correlate technical, marketing, productization, and operational aspects of a product and find optimal path to satisfy various aspects of a product. Prior experience recruiting, building, and leading successful teams with proven record of building high performing teams. Willing and able to travel both domestically and internationally. Desired Characteristics & Attributes: Excellent analytical and problem-solving skills required. Excellent written and verbal communication skills required. Proven record of leading teams to new places with combination of clarity of mind, aggressive goals, team’s trust, articulate communication. Ability to think strategically but execute tactically and understand the difference. Ability to work well with others in a fast-paced collaborative team environment. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for TPU / GPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU / /GPU. data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or GPU / TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of GPU/TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are one of 49 US AI startups that have raised $100M or more in 2024 We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12 years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are one of 49 US AI startups that have raised $100M or more in 2024 We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12 years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Large Semiconductor Service Organization with revenue over 600 Million USD Location: Hyderabad Lead Verification Engineer Experience: 7+ years Location: Hyderabad Job Description: Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure Handle regression testing and contribute to verification infrastructure development Develop both directed and random verification tests Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issues Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirement Collaborate with design, software and architecture teams to verify design under test Preferred Experience: Proficient in IP-level FPGA and ASIC verification Knowledge of PCIe, CXL or other IO protocol is preferred Proficient in Verilog/SystemVerilog, and scripting languages such as Perl or Python Hands-on experience with SystemVerilog and UVM is mandatory Experience in developing UVM-based verification testbenches, processes, and flows Solid understanding of design flow, verification methodology, and general computational logic design and verification Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

About the job Principal / Staff /Senior Analog/Mixed-Signal IC Design Engineer www.omnidesigntech.com Bangalore / Hyderabad About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Hyderabad / Bangalore SOC Development – Engineering / Full-time / Hybrid The Senior Analog IC Design Engineer will be working on one or two of the following: 1. high speed SerDes, 2. PLL, Oscillators, 3. PMU, 4. Data Converters Should be familiar with Analog design for 1 or two of the ares mentioned above Role and Responsibilities Work with chip/system architecture, physical design, and design teams to implement the SerDes, PLL, ADC, DAC, PMU modules, Data converters Work with the layout team and provide necessary inputs for correctness of high-speed layout Develop and refine specification of the micro-architecture Analyze performance, power and area tradeoffs, and make implementation choices. Work with Architecture and Design teams to ensure micro-architecture and design is fully verified/validated across multiple platforms. Provide high level circuit performance data to architecture team for closing the loop and improving the system models as applicable. Implement, verify, and validate the design. Experience and Qualifications BSEE Required, MSEE Preferred 4-12+ years of experience in the area of Analog/Mixed Signal Design and verification of silicon Experience with one of in developing, verifying, and productizing SERDES, CDR, and PLL/DLL designs Strong analytical problem solving, and attention to details Excellent technical documentation skills Excellent written and verbal communication skills Excellent interpersonal skills, self-motivated, self-starter We are looking for trailblazers ... We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Omni Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem. At Omni Design, we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring Omni Design’s vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. Omni Design is an equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com

About the job Principal / Staff /Senior Analog/Mixed-Signal IC Design Engineer www.omnidesigntech.com Bangalore / Hyderabad About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Hyderabad / Bangalore SOC Development – Engineering / Full-time / Hybrid The Senior Analog IC Design Engineer will be working on one or two of the following: 1. high speed SerDes, 2. PLL, Oscillators, 3. PMU, 4. Data Converters Should be familiar with Analog design for 1 or two of the ares mentioned above Role and Responsibilities Work with chip/system architecture, physical design, and design teams to implement the SerDes, PLL, ADC, DAC, PMU modules, Data converters Work with the layout team and provide necessary inputs for correctness of high-speed layout Develop and refine specification of the micro-architecture Analyze performance, power and area tradeoffs, and make implementation choices. Work with Architecture and Design teams to ensure micro-architecture and design is fully verified/validated across multiple platforms. Provide high level circuit performance data to architecture team for closing the loop and improving the system models as applicable. Implement, verify, and validate the design. Experience and Qualifications BSEE Required, MSEE Preferred 4-12+ years of experience in the area of Analog/Mixed Signal Design and verification of silicon Experience with one of in developing, verifying, and productizing SERDES, CDR, and PLL/DLL designs Strong analytical problem solving, and attention to details Excellent technical documentation skills Excellent written and verbal communication skills Excellent interpersonal skills, self-motivated, self-starter We are looking for trailblazers ... We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Omni Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem. At Omni Design, we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring Omni Design’s vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. Omni Design is an equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com

Senior Principal Design Verification Engineer (India)/ Principal Design Verification Engineer Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background We are one among 49 US AI startups that have raised $100M or more in 2024 We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Summary Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing. Roles and Responsibilities Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage. Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device. Define and implement infrastructure for effective HW/SW co-simulation. Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements. The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms. Skills/Qualification Proven industry experience and successful track record in verifying chip- and block-level RTL designs for high-performance networking or computing chips, such as Network Interface Controllers, Smart-NICs, DPUs, accelerators, and/or switches in advanced silicon geometries. PCIe5 /PCIe6-Transcation layer DDR4/DDR5/DDR6 Ethernet Switching SNIC/Smart-NIC Deep experience with full chip verification and infrastructure development. Strong current knowledge of UVM constructs, components, and practices. Expert knowledge of SystemVerilog, as well as Python or other scripting languages. Experience with C/C++ and general software engineering principles is highly desirable. Minimum BSEE/CE + 12-18 years or MSEE/CE + 11-17 years experience. Proven track record of design execution and quality on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Engineer – Analog Design Location: Bangalore We are a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing We are a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Engineer – Analog Design to join our memory interface chip design team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Principal Engineer – Analog Design, the candidate will be reporting to Director Engineering and is a Full-Time position. The candidate will be leading the analog mixed signal circuit design activities for high-performance mixed signal chip products. our memory interface chips team delivers the most advanced chipset solutions for server memory sub-system. This role gives opportunities to invent solutions to improve performance of next generation high-performance mixed signal products and learnings opportunities working through all the phases of chip product design all the way from concept to volume production. Responsibilities: As a “Principal Engineer – Analog Design” in memory interface chip design team, you will Ownership of Analog/Mixed designs at chip and/or block level. Define optimal architectures to achieve competitive product specifications. Design, simulate and characterize high-performance and high-speed circuits (e.g. Transmitter, Receiver, LDO, PLL, DLL, PI circuits). Create high level models for design tradeoff analysis and behavior model for verification simulations. Create floorplan and work with layout team to demonstrate post extraction performance. Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow. Mentor/Manage junior team members and cultivate a growth mindset among team to encourage collaboration & inclusion. Participate and drive post silicon validation, debug, and customer collaboration. Requirements/Qualifications: Master’s with 8+ years (or PhD with 6+ years) of experience in CMOS analog/mixed-signal circuit design. Prior experience in some of the following circuits: Transmitter, Receiver (with CTLE, DFE), PLL, DLL, PI, LDO regulators. Good knowledge of design principles for practical design tradeoffs. Knowledge of high-speed chip to chip interfaces (memory PHY, SerDes) is a strong plus. Experience in modeling (Verilog-A, Verilog) and scripting is desirable. The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Experience : 2.00 + years Salary : Confidential (based on experience) Shift : (GMT+05:30) Asia/Kolkata (IST) Opportunity Type : Remote Placement Type : Full time Permanent Position (*Note: This is a requirement for Uplers) What do you need for this opportunity? Must have skills required: Email Marketing, AMP Script, SQL Uplers is Looking for: Must-have skills required: Braze /SFMC /Klaviyo, Email Campaigns, A/B testing Good to have skills: Photoshop, Mailchimp, Data Analysis, Salesforce, Dreamweaver Job Description: Maintain and execute email marketing calendar for clients assigned, including ideation and concept campaigns, building or getting emails &/or Landing pages built, segmenting lists, deploying campaigns, and reporting results. Diligently follow the following checklist to ensure the campaigns are delivered right and are a result-driven concept, code (HTML/CSS), and test email templates for campaigns using email on acid. Create, execute and analyze A/B test plans to improve email campaign performance and conversion rates including all metrics. Develop or get developed corresponding landing pages for campaigns and thoroughly test them before deploying or passing them to clients. Measure and report on email campaign and A/B test plan performance and manage ongoing reporting for launched campaigns and work on aligning each campaign performance to the email marketing objective for each client. Assist in marketing automation campaigns, retargeting ads, list clearing, and more aspects of digital marketing. Collaborate with production teams to design and develop new assets for each touchpoint of the customer journey evaluate and improve the process of understanding the need of each client in order to deliver a delightful experience. Educational Qualifications and Skills Required: At least 2+ years of experience setting up campaigns for digital or email marketing. 2+ years of experience to build or get emails/landing pages built from team that delivers results and meets clients expectations. Worked on at least few DIY ESPs (like mailchimp, campaign Monitor, icontact) and one or two enterprise esp's like salesforce marketing cloud, marketo, eloqua, etc in setting up campaigns and creating segmentations, dynamic content and reports. Must have experience working on any one tool : Sailthru / Braze / Klaviyo. A technology savvy or minded marketer with exposure and capability of problem solving and data analysis. Good, standards-based html and css skills Exposure on setting automation and campaigns for known ESPs. Should be able to work in photoshop & dreamweaver. Responsible self-starter, innovative thinker, analytic, detail-orientated; comfortable in a metrics- driven business environment. How to apply for this opportunity? Step 1: Click On Apply! And Register or Login on our portal. Step 2: Complete the Screening Form & Upload updated Resume Step 3: Increase your chances to get shortlisted & meet the client for the Interview! About Uplers: Our goal is to make hiring reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant contractual onsite opportunities and progress in their career. We will support any grievances or challenges you may face during the engagement. (Note: There are many more opportunities apart from this on the portal. Depending on the assessments you clear, you can apply for them as well). So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

Area(s) of responsibility Java Full Stack Developer 5 to 7 years of experience in Java, core java and advance java concepts and technologies. Software development experience. Must have experience in Java (Spring Boot), Microservices. Experience in React JS Strong in writing SQL queries Expertise in relational databases. Experience in Writing Junit Test cases Nice to have experience in Cloud platform like PCF, AWS. Willing to learn new technologies and enjoys working in a dynamic fast paced environment. Have an engineering and consulting mind-set to help clients reach their transformation goals. Solid understanding of Agile methodology, estimation techniques and key ceremonies for effective management/collaboration. Has highly collaborative working style. Strong communication skills and participates actively in discussions with business customers, architects, and the team members. Skills with M/O flag are part of Specialization Programming/Software Development -PL3 (Functional) Estimation & Scheduling -PL1 (Functional) Team Management -PL1 (Functional) Software Design -PL2 (Functional) Software Configuration -PL3 (Functional) Quality Assurance -PL1 (Functional) Help the tribe -PL2 (Behavioural) Stakeholder Relationship Management -PL1 (Functional) Requirements Definition And Management -PL1 (Functional) Think Holistically -PL2 (Behavioural) Knowledge Management -PL2 (Functional) Win the Customer -PL2 (Behavioural) One Birlasoft -PL2 (Behavioural) Results Matter -PL2 (Behavioural) Get Future Ready -PL2 (Behavioural) Test Execution -PL2 (Functional) MySQL - PL2 (Mandatory) Spring Boot - PL3 (Mandatory) Java - PL3 (Mandatory) Kubernetes - PL2 (Optional) REST API's - PL2 (Mandatory) TypeScript - PL2 (Optional) React JS - PL3 (Mandatory) RxJS - PL2 (Mandatory) JavaScript - PL3 (Mandatory)

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Thu, Aug 21 at 4:49 PM Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Business Function As the leading bank in Asia, DBS Consumer Banking Group is in a unique position to help our customers realise their dreams and ambitions across 600 branches across the country. As a market leader in the consumer banking business, DBS has a full spectrum of products and services, including deposits (incl. structured solutions for NRI), investments, insurance, mortgages, credit cards and personal loans to help our customers realise their dreams and aspirations at every life stage. Job Purpose To deliver exceptional volume and revenue performance by acquiring and engaging with DBS Treasures clients having a total relationship value => INR 30 lakhs through “need-based approach” and ensure client coverage and product penetration through cross-sell and up-sell of DBS products and services. Key Accountabilities Acquire and upgrade quality Treasures clients in the branch location areas Engage with existing customers to deepen the wallet share through retention and growth of of Total Relationship Value (TRV) Accountable for achieving annual volume and revenue objective Ensure Savings Book and loan book growth Ensure proper implementation & execution of product strategies through effective relationship management Develop the client trust and loyalty for entrenched relationship with DBS through lifestyle and beyond banking propositions Drive and deliver exemplary customer service in the local market and uphold DBS service standards Ensure internal and regulatory compliance through strict adherence to DBS processes Job Duties Establish, manage and grow the TRV of the elite Treasures Client segment by acquiring and nurturing the clients having AUM => INR 10 M Ensure timely portfolio review by jointly engaging with Wealth / Investment / Insurance specialist with clients Ensure complete knowledge of all products & services through continuous skill and knowledge improvement Resolve customer queries and complaints within the agreed TAT as per the DBS customer service policy Provide feedback on market, competition, and products, suggest innovations & ideas for continuous product and service improvements Ensure internal and regulatory compliance and address operational risks if any Requirements 8years of experience in HNI Sales /Wealth Management/ Private Banking segment Sound understanding of financial planning and wealth management products in India In-depth knowledge of local market and competition AMFI / IRDAI / FEDAI certified candidates with BCSBI certification would be an added advantage Education / Preferred Qualification Graduate / Postgraduate with MBA in relevant field Core Competencies Effective probing and listening skills Strong Relationship Management and influencing skills Self-driven and ambitious Good written and verbal communication skills Results-oriented, analytical and ability to deliver results under pressure Understanding of competitive positioning Strong service orientation, customer-centric behavior DBS India - Culture & Behavior Performance through Value Based Propositions Ensure customer focus by delighting customers & reduce complaints Build pride and passion to protect, maintain and enhance DBS’ image and reputation Enhance knowledge base, build skill sets & develop competencies Execute at speed while maintaining error free operations Primary Location India-Telangana-Hyderabad-DBIL Job Relationship Management Schedule Regular Job Type Full-time Job Posting Aug 22, 2025, 10:30:00 AM

Global Technology Solutions (GTS) at ResMed is a division dedicated to creating innovative, scalable, and secure platforms and services for patients, providers, and people across ResMed. The primary goal of GTS is to accelerate well-being and growth by transforming the core, enabling patient, people, and partner outcomes, and building future-ready operations. The strategy of GTS focuses on aligning goals and promoting collaboration across all organizational areas. This includes fostering shared ownership, developing flexible platforms that can easily scale to meet global demands, and implementing global standards for key processes to ensure efficiency and consistency. Software Test Engineer The ResMed Digital Health Technology team powers digital experiences and engagement to enhance the lives of millions of people every day through connected care. This role is part of an Agile Team responsible for the digital transformation of ResMed’s Manufacturing process. The Senior Software Test Engineer is responsible for ensuring the quality of the systems & solutions provided by their team. Let’s Talk About Responsibilities Operate as part of multiple Agile Scrum team and is responsible for leading and coordinating all test efforts for a program across geographies. Define testing strategy and plans to ensure the product being released is up to industry and company standards. Provide work estimates and timely progress updates for scheduling purposes. Analyse Requirements and identify and prepare Test Scenarios/Test Cases across tech stack ( UI / API/ Database etc) and maintain requirement to test case traceability for audit.. Most of the applications will be custom applications which are heavily integrated to oracle ( For eg: manufacturing execution systems) Execute the Testcases and report Defects, lead defect management process. Document testing evidence in conformance to the QA and audit standards defined by ResMed. Status reporting of test progress and test metrics to the team and impacted stakeholders. Identifies risks, creates mitigation plans & communicates effectively as part of risk management. Plan and coordinate UAT testing with business users as needed. May be called to work out of normal hours/weekends/public holidays to support sites in other time zones . Let’s Talk About Qualifications And Experience Required: 3+ years’ dedicated software testing experience for testing SaaS application like o9, Fusion , preferably on agile projects Candidate should be Fast Learner, Independent, Self starter with positive attitude and able to work with minimum guidance. Candidate should have good functional Experience on working with custom applications heavily integrated with oracle SCM modules like Planning, Manufacturing, Work In Progress, Order Management, Inventory, BOM, Engineering, Quality for Manufacturing and in adjacent systems like MES. Experience on Supply Chain Planning, Procurement modules will be bonus. Experience in supporting ERP implementation and retrofitting objects for an upgrade/Patches. Experience on requirement and test case management tools like Jira, Zephyr Scale, Confluence, Jama etc Familiarity with entire software development life cycle and test cycles (Unit, Regression, Functional, Systems, Integration test, Stress & Scale, Smoke & Sanity, End to End test). Excellent inter-personal, communication & documentation skills (English). Familiar with industry standards, Good Manufacturing Practice, Privacy (eg. GDPR), IT security, and SOX compliance, and participates in efforts to bring IT changes into conformance with such standards . Joining us is more than saying “yes” to making the world a healthier place. It’s discovering a career that’s challenging, supportive and inspiring. Where a culture driven by excellence helps you not only meet your goals, but also create new ones. We focus on creating a diverse and inclusive culture, encouraging individual expression in the workplace and thrive on the innovative ideas this generates. If this sounds like the workplace for you, apply now! We commit to respond to every applicant.

Job Description: Senior Research Analyst – US Recruitment Support Location: Madhapur, Hyderabad Shift: Day Shift (supporting US market clients) About the Role We are looking for a highly experienced Senior Research Analyst with 8+ years of expertise in research, client analysis, and recruitment market intelligence. The ideal candidate will have a proven track record of working with non-IT clients and leveraging multiple job platforms to identify business opportunities in the US staffing and recruitment market . This role requires advanced skills in market research, data analysis, and client mapping, along with the ability to guide junior team members. Key Responsibilities Lead research initiatives to identify non-IT client job openings and market trends across the US. Utilize LinkedIn, Indeed, ZipRecruiter, Glassdoor, and other job platforms to source client information, job postings, and hiring patterns. Perform advanced data analysis using Excel (pivot tables, dashboards, trend reports) to present actionable insights. Provide detailed client research reports to support business development and recruitment strategies. Mentor and guide junior analysts in best practices for research and data management. Track competitor activities, industry trends, and provide recommendations to leadership. Collaborate closely with business development and recruitment teams to ensure research translates into successful client engagement. Qualifications & Skills Bachelor’s or Master’s degree in Business, Management, or a related field. 8+ years of proven experience as a Research Analyst, Market Research Specialist, or similar role in staffing/recruitment (US focus preferred) . Strong exposure to non-IT recruitment markets in the US. Advanced proficiency in Excel (dashboards, data analysis, reporting). Strong working knowledge of LinkedIn Recruiter, Indeed, and other major job boards . Exceptional research, analytical, and critical thinking skills. Excellent written and verbal communication skills. Leadership experience, with the ability to mentor and guide junior team members.

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Thu, Aug 21 at 4:49 PM Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Technology Expert, PCIe 7.0 & UCIe ( Senior Director level / Director ) www.omnidesigntech.com Location: Bengaluru / Hyderabad www.omnidesigntech.com Location- Bangalore About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. Job Summary: Principal SerDes Technology Expert We are seeking a highly motivated and experienced Principal SerDes Technology Expert to lead the development of next-generation connectivity solutions. Your journey will begin by spearheading the design and optimization of high-performance Active Electrical Cables (AECs), enhancing electrical integrity and signal quality across demanding link budgets. Building on this foundation, you will architect and implement SerDes technology tailored for PCIe 7.0, tackling challenges such as lane equalization, jitter tolerance, and power efficiency. Finally, your work will expand into integrating cutting-edge optical interconnects and optocouplers, driving innovations in retimer technologies and hybrid signaling frameworks. This role directly impacts the performance and reliability of AI and cloud infrastructure—empowering massive data throughput, energy-efficient links, and scalable system architectures. Responsibilities: Lead the architecture and design of high-speed SerDes for PCIe 7.0, targeting data rates of 128 GT/s and beyond. Spearhead the development and integration of advanced optical interconnects and retimer solutions within our Smart Cable Modules™. Define and specify the requirements for mixed-signal SerDes PHYs, including transmitter (TX), receiver (RX), and clock and data recovery (CDR) circuits. Conduct in-depth analysis and simulation of high-speed channel performance, including signal integrity (SI) and power integrity (PI). Collaborate with cross-functional teams, including hardware design, firmware, and system validation, to ensure successful product development and bring-up. Stay at the forefront of industry standards and emerging technologies, particularly related to PCIe, CXL, and high-speed optical interconnects. Mentor junior engineers and provide technical leadership across the organization. Work closely with partners and vendors to evaluate and select key components. Qualifications: Required Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 15-25 years years of experience in high-speed SerDes design and development. Proven expertise in PCIe protocols, with direct experience in PCIe 4.0/5.0/6.0 design and a strong understanding of the upcoming PCIe 7.0 specification. In-depth knowledge of mixed-signal design, including experience with PAM4 signaling, equalization techniques (e.g., FFE, DFE), and clocking architectures. Hands-on experience with high-speed test and measurement equipment (e.g., oscilloscopes, BERTs, VNAs). Strong understanding of signal integrity principles and experience with simulation tools (e.g., HSPICE, ADS, Ansys). Preferred Qualifications: Master's or Ph.D. in a relevant technical field. Experience with the design and integration of optical interconnects, silicon photonics, or high-speed optoelectronics. Familiarity with the design of retimers and their application in Active Electrical Cables. Experience with high-level modeling of SerDes links using tools like MATLAB or Python. Knowledge of other high-speed protocols such as Ethernet, CXL, or NVLink. A track record of leading complex projects from concept to production. Excellent communication and interpersonal skills. We are seeking a highly skilled and experienced IP Design Engineer to join our team, focusing on the design, development, and validation of cutting-edge high-speed interface Intellectual Property (IP). The ideal candidate will have a strong background in complex digital and mixed-signal design, with a particular emphasis on interfaces such as UCIe, Die-to-Die (D2D), and various memory PHYs (DDR/LPDDR). Expertise in advanced clocking architectures including PLLs and DLLs is also essential. This role involves contributing to the full IP development lifecycle, from architectural definition and RTL design to silicon validation and post-silicon support, ensuring first- pass silicon success for critical products that enable next-generation data center interconnects. Key Responsibilities: • Design & Development: Architect, design, and implement high-speed interface IPs, including UCIe, D2D, DDR, and LPDDR PHYs. Contribute to the development of high-speed SerDes IP transceivers supporting rates like 100G PAM4 (106.25 Gbps), 50G PAM4 (53.125 Gbps), and 25G NRZ (26.5625 Gbps) for applications such as PCIe, Ethernet, and data center interconnects. • Clocking Design: Develop and optimize PLL (Phase-Locked Loop) and DLL (Delay- Locked Loop) circuits for high-speed clock generation and synchronization, ensuring low jitter and high accuracy. This includes experience with Fractional/Spread-spectrum/Integer Frequency synthesizers, LC VCOs, Multi- Modulus Dividers, Charge Pumps, LPFs, LDO regulators, and BGRs. • IP Development Lifecycle: Participate in the complete IP design flow, including architectural definition, specification development, RTL coding, synthesis, static timing analysis (STA), and collaborating on physical design activities (GDSII). 1 • Verification & Validation: Work closely with verification teams to define test plans, debug complex design issues, and lead pre-silicon and post-silicon validation efforts, including silicon bring-up and characterization .2 Implement features for deep in-cable diagnostics (e.g., eye metric readout, PRBS bit error rate, loopback modes), fleet management, and security for robust interconnect solutions. • Analog/Mixed-Signal Integration: Collaborate on the integration of analog and mixed-signal blocks within the PHYs, addressing complex integration challenges and optimizing for performance, power, and area (PPA). • Documentation: Create comprehensive design specifications, integration guidelines, and application notes for IP blocks.• Problem Solving: Debug and resolve complex design issues at various stages of the development cycle, including silicon debugging and fault isolation. • Standards Compliance: Ensure IP designs comply with industry standards (e.g., JEDEC for DDR/LPDDR, QSFP-DD/OSFP mechanical and common management interface specifications) and customer requirements. • Performance Optimization: Focus on achieving low-latency data paths (< 100 ns) and optimizing for lower power consumption in high-speed interconnect solutions. Required Qualifications: • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.3 • 15-25 years of experience in digital, mixed-signal, or analog IP design within the semiconductor industry. (Adjust X based on Senior/Principal level). • Proven experience with high-speed interface designs such as UCIe, D2D, DDR PHY, or LPDDR PHY. • Demonstrated experience in the design and optimization of PLLs and/or DLLs, including various types of frequency synthesizers and clock generation circuits. • Familiarity with the entire IP development flow from architectural concept to silicon validation. • Strong understanding of signal integrity, power integrity, and layout considerations for high-speed designs, especially for PAM4 and NRZ signaling over copper cables. • Proficiency with industry-standard EDA tools for design, simulation, and analysis. • Experience with deep diagnostic features, security implementations (firmware security, unauthorized access prevention), and non-disruptive firmware updates for high-speed modules. • Excellent problem-solving skills and attention to detail. • Strong communication and collaboration skills to work effectively with cross- functional teams. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"