CPU Physical Design Verification(PDV) Engineer

General Summary:

Minimum Qualifications:

Job Overview:

This position centers onfloor-planning expertise at both block and top levelsfor industry-leadingCPU core designs, with a strong emphasis on scalability and achieving aggressivePower, Performance, and Area (PPA)targets. The role involves working oncutting-edge technology nodesand applyingadvanced physical design techniquesto push the boundaries of CPU performance and efficiency.

Preferred Qualifications:

• Masters degree in Electrical/Computer Engineering
• 8+ years of direct top level floor-planning large and high frequency IP experience
• In depth end to end experience from RTL2GDS, taping out at least 5 complex designs
• Direct hands-on experience with bus/pin/repeater planning for entire IP

Key responsibilities include:

• Drivingfloorplan architecture and optimizationin collaboration with PD/RTL teams to maximize PPA
• Engaging incross-functional collaborationwith Physical design, timing, power, and packaging teams to ensure holistic design convergence
• Partnering withEDA tool vendorsand internal CAD teams to develop and enhanceautomation flows and methodologiesfor improved design efficiency
• Makingstrategic trade-offsin design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets
• End to End Physical verification closure for subsystem.

The ideal candidate will have/demonstrate the following:

• Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs
• Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler.
• Must have good knowledge of static timing analysis, reliability, and power analysis
• Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs
• Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks
• Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance
• Solid working knowledge of scripting skills including tcl, perl or python
• Excellent communication skills and collaborating in a team environment is a must
• Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool)
• Experience in IO, Bump planning and RDL routing Strategy.

Preferred Skills:

• Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure
• Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks
• Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff
• Hands on experience working with very complex designs that push the envelope of Power, Performance and Area
• Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous
• Hands on experience on Innovus/FC tool based scripting & python/TCL scripting.
• Prior experience in flow and methodology development is an advantage
• Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs
• Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams

Minimum Qualifications:

• Bachelors degree in Electrical/Computer Engineering
• 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level
• Strong background in VLSI design, physical implementation and scripting
• Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools
• Hands on experience taping out designs in sub-micron technology node design less than 10nm
• Expect strong self-motivation and time management skills