VHDL / FPGA Engineer

Candidates,

Hungry Bird IT Consulting Services Pvt. Ltd.

VHDL / FPGA Engineer

Job Title:

Location: Jublihills, Hyderabad

Job Summary:

Our client, We are seeking a highly skilled and motivated FPGA / VHDL Engineer to join our team in designing high-performance digital blocks for advanced communication coding systems. The ideal candidate will have strong expertise in RTL design using VHDL, along with hands-on experience in simulation, synthesis, timing closure, and SoC integration, especially using Xilinx Vivado and Zynq SoC platforms.

Responsibilities:

• Design and implement high-performance digital blocks for complex communication coding using VHDL.
• Perform RTL development including writing, simulating, debugging, and verifying VHDL code.
• Develop and apply timing constraints, and perform timing analysis using state-of-the-art tools like Xilinx Vivado.
• Create and maintain testbenches for module-level and system-level verification.
• Participate in architectural design, specifications, and documentation for FPGA modules.
• Conduct block and top-level design verification to ensure correctness and compliance.
• Work on SoC integration, including processor cores and standard peripheral interfaces.
• Debug complex issues at the HDL level and drive root cause analysis and resolution.
• Collaborate cross-functionally with hardware and embedded software teams.
• Ensure design quality, performance, and reusability across projects.

Required Skills:

• Strong experience in VHDL-based RTL design and verification.
• Proficient in using simulation tools and writing efficient testbenches.
• Hands-on experience with Xilinx Vivado, including synthesis, implementation, and timing closure.
• Experience with developing and debugging timing constraints (XDC).
• Exposure to communication protocols and coding algorithms is highly desirable.
• Solid understanding of SoC architectures, particularly Xilinx Zynq SoC.
• Experience in integrating processor cores (e.g., ARM) with standard peripherals.
• Proven ability to debug complex HDL designs and resolve functional and timing issues.
• Strong documentation and communication skills.

Preferred Qualifications:

• Experience with other HDLs (e.g., Verilog), scripting languages (TCL, Python).
• Familiarity with version control systems like Git.
• Knowledge of high-speed interfaces and memory subsystems.

aradhana@hungrybird.in or call on 9959417171.)

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Aradhana,

+91 9959417171.