8 Testbench Jobs

The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. KEY RESPONSIBILITIES: Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers. PREFERRED EXPERIENCE: Proficient in IP or Sub-system level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Experience in UVM TestBench Development for complex designs preferred. Experience in RAL is preferred

You are a highly motivated and energetic individual with a team-oriented approach, responsible for driving roadmaps in the IP/Subsystem domain. Your role involves delving deep into logic design, architecting, and developing complex IPs/Subsystems solutions. Working closely with a team of global experts in Systems and SoC Design functions, you will lead or address design/architectural challenges within the context of complex IPs and overall system level solutions. Your tasks will range from developing high-level specifications to actual design implementation. Your key responsibilities include owning and driving roadmaps for the complete IP/Subsystem domains portfolio within the global R&D team. You will perform benchmarks against other industry players to ensure differentiating features for customers with a high level of innovation. Architecting and designing complex IPs and Subsystems across various protocols required for Edge processing, Automotive Self-Driving Vehicles, In-Vehicle experience, Gateway Systems, Fail-Safe Subsystems (ASIL-D), etc., will be part of your role. You will be responsible for leading IPs/Subsystems from concept to design and development, achieving final design performance in an integrated system within aggressive, market-driven schedules. Ensuring quality adherence throughout the IP development cycle, analyzing existing processes, recommending and implementing process improvements, and driving and mentoring teams towards achieving Zero Defect designs are crucial aspects of your role. Additionally, you will be responsible for owning and driving global IP design methodologies across sites with global stakeholders. As a self-starter with over 18 years of experience, you should be able to architect and design complex IP designs/Subsystems with minimal supervision. Your expertise should include custom processor designs with key DSP functions, processor designs like RISC-V Core, cache-based subsystems, high-speed serial protocols, and associated challenges, understanding of key external memory interface protocols, microcontroller architecture, bus protocols, HDLs, scripting languages, and C/C++ for hardware modeling. Knowledge of end-to-end IP development flow, testbench and testplan development, and pre-silicon validation using FPGA/Emulation Board would be advantageous. In terms of soft skills, you should possess proficient skills in both written and verbal communication, with the ability to articulate well. Demonstrating a sense of ownership, engaging everyone with trust and respect, showcasing emotional intelligence, and embodying leadership values are essential for success in this role. You should have the ability to work effectively as part of a team, whether local, remote, or multisite.,

Hi all , we are looking for semiconductor design engineer exp : 3 - 5 years location : Hderabad type : contractual NP : immediate - 15 days contact : akram.m@acesoftlabs.com Description: Performs semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor devices and components. 3-5 years of experience • Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. • Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. • Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. • Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. • Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. • Experience with Gate Level Simulations and timing debugs. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.

THE ROLE: The ideal candidate will get to work on Verification of complex Analog Mixed Signal IPs (with significant Digital and Analog content) that are delivered to various AMD SoCs. KEY RESPONSIBILITIES: Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage:code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. PREFERRED EXPERIENCE: Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions Expertise in code and functional coverage, Excellent Problem solving and debugging skills. Excellent Communication skills Strong digital design knowledge, SoC design flow Knowledge on AMS designs (SERDES or Memory PHYs such as DDR, GDDR) and Mixed signal verification methodology is an added advantage. UPF based RTL low power verification Prior experience in working on IPs with mixed signal content will be helpful. Prior experience of technical leadership will be an asset. ACADEMIC CREDENTIALS: Bachelor or Masters degree in ECE/EEE desired with 15+ years exp

Hello Candidates, Greetings from Hungry Bird IT Consulting Services Pvt. Ltd. We are hiring for VHDL / FPGA Engineer for one of our client. Job Title: VHDL / FPGA Engineer Location: Jublihills, Hyderabad Job Summary: Our client, We are seeking a highly skilled and motivated FPGA / VHDL Engineer to join our team in designing high-performance digital blocks for advanced communication coding systems. The ideal candidate will have strong expertise in RTL design using VHDL, along with hands-on experience in simulation, synthesis, timing closure, and SoC integration, especially using Xilinx Vivado and Zynq SoC platforms. Responsibilities: Design and implement high-performance digital blocks for complex communication coding using VHDL. Perform RTL development including writing, simulating, debugging, and verifying VHDL code. Develop and apply timing constraints, and perform timing analysis using state-of-the-art tools like Xilinx Vivado. Create and maintain testbenches for module-level and system-level verification. Participate in architectural design, specifications, and documentation for FPGA modules. Conduct block and top-level design verification to ensure correctness and compliance. Work on SoC integration, including processor cores and standard peripheral interfaces. Debug complex issues at the HDL level and drive root cause analysis and resolution. Collaborate cross-functionally with hardware and embedded software teams. Ensure design quality, performance, and reusability across projects. Required Skills: Strong experience in VHDL-based RTL design and verification. Proficient in using simulation tools and writing efficient testbenches. Hands-on experience with Xilinx Vivado, including synthesis, implementation, and timing closure. Experience with developing and debugging timing constraints (XDC). Exposure to communication protocols and coding algorithms is highly desirable. Solid understanding of SoC architectures, particularly Xilinx Zynq SoC. Experience in integrating processor cores (e.g., ARM) with standard peripherals. Proven ability to debug complex HDL designs and resolve functional and timing issues. Strong documentation and communication skills. Preferred Qualifications: Experience with other HDLs (e.g., Verilog), scripting languages (TCL, Python). Familiarity with version control systems like Git. Knowledge of high-speed interfaces and memory subsystems. (Interested candidates can share their CV to aradhana@hungrybird.in or call on 9959417171.) Please furnish the below-mentioned details that would help us expedite the process. PLEASE MENTION THE RELEVANT POSITION IN THE SUBJECT LINE OF THE EMAIL. Example: KRISHNA, HR MANAGER, 7 YEARS, 20 DAYS NOTICE Name: Position applying for: Total experience: Notice period: Current Salary: Expected Salary: Thanks and Regards Aradhana, +91 9959417171.

Description We are seeking a highly skilled PCIe Protocol Engineer with 5-8 years of experience to join our team in India. The ideal candidate will have a strong background in PCIe protocols and a proven track record in designing, implementing, and verifying PCIe-based solutions. Responsibilities : 1) Experience of around 5 to 8 years. 2) PCIe Protocol Expertise. 3) Gen-6 Experience with PCIe gen 5 or 6 hardware and/or device drivers for Linux. 4) Very Strong C/C++ development skills in Linux and embedded environments. 5) Linux Kernel Development: Proficiency in Linux kernel internals, including writing and debugging kernel modules and drivers, especially for PCIe devices. 6) Knowledge of PCIe bus link aggregation. 7) Experience with ARM and x86 processors in embedded Linux system design and development, including firmware development for PCIe devices. Skills and Qualifications : Bachelor's or Master's degree in Electrical or Computer Engineering 5-8 years of experience in PCIe protocols and interfaces Strong understanding of PCIe 3.0 and 4.0 specifications Experience in designing and implementing PCIe-based solutions Experience in using PCIe test equipment such as protocol analyzers and traffic generators Strong programming skills in C/C++ and scripting languages such as Python Excellent problem-solving skills and attention to detail Good communication and interpersonal skills

As a Hardware Engineer at IBM, you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today's market. Your Role and Responsibilities As a Hardware Engineer, you will be responsible for: Understanding design specifications, PowerOn specifications, and Power management specifications. Understanding boot firmware and reset flow, and/or power management flow. Developing and successfully applying skills in IBM BIST (Built-In Self-Test) verification tools. Developing the verification environment and test bench. Debugging failures using waveform, trace tools, and debugging RTL code. Working with the Design team to resolve/debug logic design issues and being responsible for deliveries. Required Education Bachelor's Degree Preferred Education Master's Degree Required Technical and Professional Expertise 3-6 years of experience in Design Verification, with demonstrated execution experience of verification of logic blocks. Strong in SoC verification, specifically: Chip reset sequence and initialization. And/or Power management. Knowledge of verification methodology (any) and HDLs (Verilog, VHDL). Good programming skills in C/C++, Python/Perl. Exposure to developing testbench environments, writing complex test scenarios, debugging, and triaging failures. Hardware debug skills backed by relevant project experience. Good communication skills and the ability to work effectively in a global team environment. Driving verification coverage closure. Preferred Technical and Professional Experience Knowledge of Chip-Initialization, SCAN, BIST is a plus. Scripting expertise backed by relevant experience. Writing Verification test plans. Functional and code coverage analysis and debug.

Mirafra is Hiring! OnsiteOpportunity #JoinUs Location: Any European Location (Germany, Romania Preferred) Notice Period: Immediate to 45 Days Visa : Sponsorship Available (Open to candidates from India) Exp: 7+ yrs We're looking for talented professionals with hands-on experience in Specman and NVM Digital Verification to join our global team. Key Skills: Verification planning and testbench creation Datapath, ECC, FSMs, FPGA models, and full-custom assertions Strong documentation and review presentation abilities Looking for a chance to work abroad and take your career to the next level? This is it! Apply now share your resume at: swarnamanjari@mirafra.com