Senior Fpga Design Engineer ( RTL & Verilog)

10 - 15 years

20 - 35 Lacs

hyderabad bengaluru

Posted:20 hours ago| Platform: Naukri logo

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Skills Required

fpga design spyglass verilog lint rtl design xilinx

Work Mode

Work from Office

Job Type

Full Time

Job Description

  • Strong experience into FPGA Design 
  • Strong in SV & Verilog, etc. 
  • Hands on experience in RTL coding, Spyglass, Lint, design knowledge, STA, etc.... 
  • Added advantages if they worked telecommunication domain (5G, Radio Subsystems, AMS etc.), any Scripting Knowledge 
  • Added advantages if they know APB, AHB, AXI, Ethernet, PCIe etc... 
  • Knowledge in debugging using inbuilt logic analyzers 
  • Expertise in setting up and using tools like Intel, Xilinx/AMD FPGA tools 
  • Added Advantages if they know Agile way of working. 
  • Good Communication Skills  

Good Knowledge in RTL FPGA design using Verilog/System Verilog 

  • Good Knowledge in FPGA device architecture 
  • Good knowledge in FPGA clock structure  
  • Good Knowledge in RTL quality checks (Lint, CDC,RDC) 
  • Good Knowledge of synthesis , Place and Route and STA 
  • Good understanding of bus protocols (AXI, AvMM, AHB) 
  • Good Knowledge of slow speed protocols : I2C, SPI, UART MDIO etc.. 
  • Good Knowledge in PCIe IP usage  
  • Good knowledge in error detection and correction  
  • Knowledge in constraints 
  • Knowledge in debugging using inbuilt logic analyzers 
  • Knowledgein FPGA tools like : Lattice Radiant (Must). Intel, Xilinx/AMD FPGA tools  
  • Basic Understanding of scripting languages like Make flow, Perl, shell, python etc 
  • Able to review design documentsfor FPGA validation team 
  • Knowledge in Agile Methodology, GIT 

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