FPGA Design engineer (Verilog RTL based IP design)

ssential duties and responsibilities:

• Understand system requirements, generating system and RTL design document.
• RTL Development and develop test bench to support the verification and validation of sub system and RTL modules.
• Deliver test specifications document and test objectives.
• Align the development and validation process with cross-functional teams.
• Create internal and external specifications & user documents.
• Learn constantly, dive into new areas with unfamiliar technologies, and embrace the ambiguity of problem-solving.
• Apply critical thinking to the results/data of competitive analysis for product development.
• Work with cross-functional teams, including ASIC, Firmware, and Validation, to ensure seamless product development. 

Qualifications:

REQUIRED:

• Experience with micro architecture FPGA  systems, IP Integration to implementation, Verilog RTL based IP design, Verilog/System Verilog  based testbench  development
• Experience with AMD Vivado & Vitis SDK & VItis AI tools.
• Experience with C/C++ in developing Embedded FW & scripting automation using Python
• Experience with Petalinux build flow , familiarity with Uboot, linux driver changes and FPGA SoC debugging.
• Proven ability to work as part of a global team in multiple geographies
• B.Tech. in  Electronics , Electrical , Computer Science  Engineering
• Requires 8-10 years of experience in FPGA/RTL & TestBench/ embedded systems architecture
• Multi-disciplinary experience, including Firmware, HW, and ASIC/FPGA design

PREFERRED:

• Knowledge of FPGA Chip to Chip interfacing & AMD FPGAs is an advantage
• Knowledge of PCIe Gen4/5/6 technology is an advantage
• Previous experience with storage systems, protocols, and NAND flash strong advantage

SKILLS:

• Capable of developing wide system view for complex embedded systems
• Excellent interpersonal skills
• Strong can-do attitude